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CML Microcircuits
COMMUNICATION SEMICONDUCTORS
D/881/7 March 2004
CMX881
Baseband Processor for PMR and Trunked Radios
Provisional Issue
Full-Feature Audio-Processing, Signalling and Data for Half Duplex Dual-Mode Analogue PMR and Trunked Radios
Features
* Automatic signal type scanning and IRQ on detection of valid Rx signals, level or RSSI * Tone generator for caller recognition tunes * Programmable powerdown control * Programmable signal detection thresholds * Low Power operation with `Zero Power' mode * Uncommitted Aux ADC with switchable input to monitor signals * Meets ETS 300 086, MPT1327, PAA1382 and ETS 300 230 specifications * Voice processing facilities, including Tx and Rx gain setting and voice/subaudio filtering * C-BUS serial host interface * RF interface allowing 1 or 2 point modulation * Programmable soft limiter * Enhanced CTCSS and 23/24 bit DCS codecs * Zero `Talkdown' CTCSS decoder performance prevents dropouts * DTMF transmitter * Programmable Selcall codec
* Robust half-duplex FFSK/MSK modem, 1200/2400bps with CRC and parity generator/checker, gets data through when signal is too degraded for voice - for text messaging/paging, location transfer, etc. applications.
1.1
Brief Description
CMX881, a full-function half-duplex audio and signalling processor IC for both PMR and Trunked radio systems suitable for complex and simple end-designs. Under the control of the host C, all voiceband requirements are catered for: voiceband and sub-audio filtering, pre/de-emphasis and audio routing and global level setting with single or two-point modulation in the transmit path. The combination of CTCSS and DCS functions and Selcall operation of this product offer, under software control, increased functionality, versatility and privacy. To cater for call setup and system signalling the CMX881 provides an embedded 1200/2400 bps MSK/FFSK free-format modem for text messaging/paging, passing GPS location data with checksum generation and reception and sync detection in the Rx path.
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With ultra low power requirements and graduated powersave, this product requires a smaller, lowerpower C than existing PMR or trunked radio solutions. It is available in compact SSOP and TSSOP packages.
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CMX881 Functions and Facilities
Half Duplex Operation
Working in a half duplex mode, when the product is in Tx the Rx sections can be powered down to extend battery life, conversely in Rx major sections of the Tx can be treated in the same manner.
Serial Control and Data Interface
C-BUS: Serial control, data and command program interface compatible with SCI, SPI and Microwire type interfaces.
Power Requirements and Economy
With an ultra low power requirement, the CMX881 operates from a single 2.7 to 5.5 Volt supply with graduated `Sleep Mode' powersaving facilities for both Rx and Tx modes.
Signalling: CTCSS
Zero `Talkdown' performance eliminates unwanted breaks in communication. The CMX881 is preprogrammed with 39 standard CTCSS (+ Notone and DCS `turn off' tone) frequencies, any one of which can be selected for reception or transmission. Decoding is aided by the use of adjustable decode bandwidths and threshold levels. Decoding is carried out rapidly thus avoiding the loss of the beginning of speech or data signals.
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DCS
The DCS code is in NRZ format and is transmitted at 134.4b/s in either 23 or 24 bit patterns. The code, for transmission or reception is programmed via the host C with the `turn off' tone being supplied from the CTCSS facility. Decoding is carried out rapidly thus avoiding the loss of the beginning of speech or data signals.
Selcall
This product implements a fully programmable Selcall encoder and decoder employing normal and special tones. Tone frequencies, decoder bandwidths and thresholds are programmed by the host C. In receive the CMX881 scans its internal tone table for a match, reporting its results to the C.
FFSK/MSK Data
An MPT packet and free-format half duplex FFSK/MSK modem is implemented. In receive this device can decode data at either automatic or manually selected 1200b/s or 2400b/s rates. Additionally, in receive, a 16-bit programmed frame sync (MPT packet-type) pattern can be detected. Formatting control and data transfers to and from the modem is under the control of the host C.
DTMF Tx
The CMX881, under C control, can generate and transmit all standard DTMF tone-pairs.
Signal Monitor
An auxiliary circuit intended for the monitoring of any signal or level; both internal and external. This function can be used in conjunction with the host C to allow such activities as: VOX operation and/or the `wake-up' of powered-down circuitry.
Audio Processing: Adjustable Gain Input Amplifiers
Selectable, component adjustable inputs are available for microphone or line voiceband or discriminator inputs. In either mode (Tx or Rx) the selected input can be further level adjusted under the control of the host C prior to signal- or audio- processing.
Voiceband and Sub-Audio Filtering with Limiting
Both Rx and Tx paths present voiceband filtering; the Tx path filter can be configured to either 12.5 or 25 kHz channel spacing whilst the Rx path also includes a sub-audio passband filter.
Voiceband Pre-emphasis and De-emphasis
Voiceband pre-emphasis is selectable to either 12.5 or 25 kHz channel configurations in the Tx path; deemphasis at -6dB/ octave is selectable in the Rx path.
Software Adjustable Gains, Volume, Mixing and Routing
Providing total flexibility of operation, this product, under C control has the ability to select and route functions and audio and signal paths, set bandwidths and threshold levels, mix audio and sub bands and vary both input and out gain/attenuation levels. Output levels from all analogue ports can be `ramped' up and down at independently programmed rates.
Attenuation-Adjustable Single/Two-Point Modulation Outputs
To facilitate a wide range of transmitter types, the CMX881 has the ability to provide, independently programmable, modulation outputs; for single or two-point modulation schemes.
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CONTENTS Section 1.0 1.1 1.2 1.3 1.4 Page Features........................................................................................................................1 Brief Description............................................................................................................1 Block Diagram...............................................................................................................7 Signal List .....................................................................................................................8 External Components .................................................................................................. 10 1.4.1 PCB Layout Guidelines and Power Supply Decoupling ................................... 11 1.4.2 Modulator Outputs .......................................................................................... 12 General Description..................................................................................................... 13 1.5.1 Sleep Mode and Auto Start Up........................................................................ 14 1.5.2 Auxiliary ADC ................................................................................................. 14 1.5.3 Receive Mode................................................................................................. 15 1.5.4 Transmit Mode................................................................................................ 22 1.5.5 FFSK/MSK Data packeting ............................................................................. 26 1.5.6 C-BUS Operation ............................................................................................ 28 C-BUS Register Description ........................................................................................ 29 Application Notes ........................................................................................................ 47 1.7.1 CRC and Parity information ............................................................................ 47 Performance Specification........................................................................................... 48 1.8.1 Electrical Performance.................................................................................... 48 1.8.2 Packaging....................................................................................................... 58 Page Concurrent Rx Signalling Modes Supported by the CMX881 ....................................... 15 CTCSS Tones ............................................................................................................. 18 DCS Modulation Modes............................................................................................... 18 DCS 23 Bit Codes ....................................................................................................... 19 Selcall Tones .............................................................................................................. 20 Concurrent Tx Modes Supported by the CMX881 ........................................................ 22 Data Frequencies for each Baud Rate ......................................................................... 25 DTMF Tone Pairs and Corresponding Tx Programming Codes ................................... 26 Maximum Data Transfer Latency................................................................................. 27 Page
1.5
1.6 1.7 1.8
Table Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Figure
Figure 1 Block Diagram ............................................................................................................. 7 Figure 2 Recommended External Components ........................................................................ 10 Figure 3 Power Supply Connections and De-coupling .............................................................. 11 Figure 4 Modulator output components to achieve -100dB/decade roll-off................................ 12 Figure 5 Rx Audio Filter Frequency Response ......................................................................... 16 Figure 6 De-emphasis Curve for TIA/EIA-603 Compliance....................................................... 16 Figure 7 Low Pass Sub-Audio Band Filter for CTCSS and DCS ............................................... 17 Figure 8 25kHz Channel Audio Filter Response Template........................................................ 23 Figure 9 12.5kHz Channel Audio Filter Response Template..................................................... 23 Figure 10 Audio Frequency Pre-emphasis Template ................................................................ 24 Figure 11 Modulating Waveforms for 1200 and 2400 Baud FFSK/MSK Signals....................... 25 Figure 12 C-BUS Transactions................................................................................................. 28 Figure 13 Possible PMR Configuration..................................................................................... 47 Figure 14 C-BUS Timing.......................................................................................................... 56
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Figure 15 Typical FFSK/MSK Bit Error Rate Graph.................................................................. 57 Figure 16 Mechanical Outline of 28-pin SSOP (D6): Order as part no. CMX881D6 .............. 58 Figure 17 Mechanical Outline of 28-pin TSSOP (E1): Order as part no. CMX881E1 ............ 58
It is always recommended that you check for the latest product datasheet version from the Datasheets page of the CML website: [www.cmlmicro.com].
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1.2
Block Diagram
Figure 1 Block Diagram
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1.3
Signal List
Signal Name VDD(D) Type Power The digital positive supply rail. This pin should be decoupled to VSS(D) by a capacitor mounted close to the device pins. The negative supply rail (digital ground). The analogue positive supply rail. Levels and thresholds within the device are proportional to this voltage. This pin should be decoupled to VSS(A) by a capacitor mounted close to the device pins. The negative supply rail. Both pins must be connected to analogue ground. No connection should be made to these pins. A 'wire-Orable' output for connection to the Interrupt Request input of the host. This output is pulled down to VSS(D) when active and is high impedance when inactive. An external pull-up resistor is required. The C-BUS serial data output to the host. This output is held at high impedance when not sending data to the host. The C-BUS serial clock input from the host. The C-BUS serial data input from the host. The C-BUS data loading control function. Data transfer sequences are initiated, and completed by the CSN signal. Description
Package D6, E1 Pin No. 23
5 18
VSS(D) VDD(A)
Power Power
9, 21 1, 2 3
VSS(A)
Power NC
IRQN
O/P
4 6 7 8
REPLY_DATA SERIAL_CLOCK CMD_DATA CSN
T/S I/P I/P I/P
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1.3
Signal List (continued)
Signal Name VBIAS Type O/P Internally generated bias voltage of approximately VDD(A)/2, except when bias is power-saved when VBIAS will discharge to VSS(A). This pin should be decoupled to VSS(A) by a capacitor mounted close to the device pins. Input terminal of discriminator input amplifier. Output / feedback terminal of discriminator input amplifier. Input terminal of amplifier 2, for either a second microphone or discriminator input. Output / feedback terminal of input amplifier 2. Input terminal of microphone input amplifier. Output / feedback terminal of microphone input amplifier. Signal Monitor input to the internal level detecting circuit. Modulator 1 output. Modulator 2 output. Output of the audio section. The input to the on-chip oscillator for an external crystal or a clock circuit. Buffered (un-inverted) clock output available for use by other devices in the system. Test input, connect to VSS(D). No connection should be made to these pins. Description
Package D6, E1 Pin No. 10
11 12 13 14 15 16 17 19 20 22 24 25 26 27, 28
DISC DISC_FB INPUT_2 INPUT_2_FB MIC MIC_FB SIG_MONITOR MOD_1 MOD_2 AUDIO CLOCK/XTAL CLOCK_OUT
I/P O/P I/P O/P I/P O/P I/P O/P O/P O/P I/P O/P I/P NC
Notes: I/P O/P T/S NC
= = = =
Input Output 3-state Output No Connection
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1.4
External Components
VDD(D) R1 NC NC IRQN REPLY_DATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C6 28 27 26 25 24 NC NC VSS(D) CLOCK_OUT CLOCK/XTAL VDD(D) AUDIO VSS(A) MOD_2 MOD_1 VDD(A) SIG_MONITOR MIC_FB MIC C7 R7 R8 C9* D1* R9* R10* C10* VSS(A) R3 R4 C1 C3 Modulator reference Modulator control C4 R2 C2 Loudspeaker amp VSS(D) X1
C-BUS Interface
VSS(D) SERIAL_CLOCK CMD_DATA
CMX881
23 22 21 20 19 18 17 16 15
Discriminator
C8 C5
CSN VSS(A) R5 VBIAS DISC DISC_FB R6 INPUT_2 INPUT_2_FB
Microphone
VSS(A)
Figure 2 Recommended External Components R1 R2 R3 R4 R5 R6 R7 R8 100k 100k 100k 100k See note 2 100k See note 3 100k R9 R10 C1 C2 C3 C4 C5 See note 6 See note 6 100pF 1nF 100pF 100pF 100pF C6 C7 C8 C9/10 X1 D1 See note 4 200pF See note 4 See note 6 18.432MHz See note 6 See note 1
Resistors 5%, capacitors and inductors 20% unless otherwise stated. Notes: 1. X1 can be a crystal or an external clock generator; this will depend on the application. The clock drift requirement is defined in section 1.8.1. The tracks between the crystal and pin 24 and pin 5 should be as short as possible to achieve maximum stability and best start up performance. 2. R5 should be selected to provide the desired dc gain (assuming C8 is not present) of the discriminator input, as follows: GAINDisc = 100k / R5 The gain should be such that the resultant output at the DISC_FB pin is within the discriminator input signal range specified in section 1.8.1. 3. R7 should be selected to provide the desired dc gain (assuming C6 is not present) of the microphone input, as follows: GAINMic = 100k / R7 The gain should be such that the resultant output at the MIC_FB pin is within the microphone input signal range specified in section 1.8.1. C6 and C8 should be selected to maintain the lower frequency roll-off of the microphone and discriminator inputs as follows: C6 = 30nF x GAINMic 5. and C6 > 1000F / R7 C8 = 100nF x GAINDisc and C8 > TBAF / R5 INPUT_2 and INPUT_2_FB connections allow the user to have a second discriminator or microphone input. Component connections and values are as for the networks around pins 11 and 12 or pins 15 and 16 respectively. If this input is not required pin 13 must be connected to pin 14. The circuit formed by D1, C9, C10, R9 and R10 is a peak detector, this is only required when the signal monitor is connected to an ac signal (e.g. microphone or received signal). For a dc type
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6.
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signal (e.g. RSSI) these components are not required. The values of C9 and R10 set the attack time, C9 and R9 set the decay time. D1 can be any suitable small signal diode. R10 should be a high enough value so as not to distort the signal source. 1.4.1 PCB Layout Guidelines and Power Supply Decoupling
Digital Ground 1 2 3 4 VSS(D) 5 6 provision for wire link VSS(A) VBIAS C15 7 8 9 10 11 12 13 14 28 27 26 25 24 L1 VDD(D) Digital +ve Supply C11 C12 Digital ground plane
+
Clock Output
CM X881
23 22 21 20 19 18 17 16 15
VSS(A) C13 C14
Analogue Ground
+
VDD(A)
L2 Analogue +ve Supply
Analogue ground plane
Figure 3 Power Supply Connections and De-coupling C11 C12 C13 10nF 10F 10nF C14 C15 10F 100nF L1 L2 100nH 100nH See note 7 See note 7
Resistors 5%, capacitors and inductors 20% unless otherwise stated. Notes: 7. The inductors L1 and L2 can be omitted but this may degrade system performance. It is important to protect the analogue pins from extraneous inband noise and to minimise the impedance between the CMX881 and the supply and bias de-coupling capacitors. The de-coupling capacitors C11, C12, C13 and C14 should be as close as possible to the CMX881, particularly C11 and C13. It is therefore recommended that the printed circuit board is laid out with separate ground planes for the VSS(A) and VSS(D) in the area of the CMX881, with provision to make a link between them close to the CMX881. VBIAS is used as an internal reference for detecting and generating the various analogue signals. It must be carefully decoupled, to ensure its integrity, so apart from the decoupling capacitor shown, no other loads should be connected. If VBIAS needs to be used to set the discriminator mid-point reference, it must be buffered with a high input impedance buffer. The single ended microphone input(s) and audio output must be ac coupled as shown, so their return paths can be connected to VSS(A) without introducing dc offsets. Further buffering of the audio output is advised. The crystal X1 can be replaced with an external clock source if required/desired. The internal clock generating circuit can be placed in power-save mode if the clock is provided externally.
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1.4.2 Modulator Outputs The combination of CMX881 and the modulator output components, R3/C3 and R4/C4, achieve roll-off rates better than -60dB/decade. If required this can be increased to better than -100dB/decade by replacing R3/C3 and R4/C4 with the active filter circuit shown in Figure 4.
C17/C19
MOD_1 & 2 + R11/R13 R12/R14 C16/C18 VSS(A) Modulator 1 & 2
Figure 4 Modulator output components to achieve -100dB/decade roll-off R11 R12 R13 R14 120k 120k 120k 120k C16 C17 C18 C19 220pF 440pF 220pF 440pF (2 x C16) (2 x C18)
Resistors 5%, capacitors and inductors 20% unless otherwise stated. Notes: 8. The external op-amp must be chosen to ensure that the required signal output level can be driven within acceptable distortion limits.
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1.5
General Description
The CMX881 is intended for use in half duplex analogue two way land mobile radio (LMR) equipment and is particularly suited to multi standard PMR systems. The CMX881 provides radio signal encoder and decoder functions for: Voice, Selcall, Tx DTMF, CTCSS, DCS and FFSK/MSK data permitting simple to sophisticated levels of tone control and data transfer. Power control facilities allow the device to be placed in varying levels of sleep allowing the user to fine tune the power depending on system requirements. The CMX881 includes a crystal clock generator, with buffered output, to provide a common system clock if required. A block diagram of the CMX881 is shown in Figure 1. Tx functions Audio o Single/dual microphone inputs with input amplifier and programmable gain adjustment o Filtering selectable for 12.5kHz and 25kHz channels o Selectable pre-emphasis o 2-point modulation outputs with programmable level adjustment Signalling o Pre-programmed 39 tone CTCSS encoder o Programmable 23/24bit DCS encoder o Programmable audio tone generator (for custom audio tones) o Programmable Selcall encoder o DTMF encoder o 1200/2400bps MSK modulator Rx functions Audio o Single/dual demodulator inputs with input amplifier and programmable gain adjustment o Voice-band and sub-audio rejection filtering o Selectable de-emphasis o Software volume control Signalling o 1 from 39 CTCSS decoder + Tone Clone mode o 23/24bit DCS decoder o Programmable Selcall decoder o 1200/2400bps MSK demodulator and 16-bit frame sync detector o Signal Monitor (RSSI / Microphone / Rx channel level monitor) Host Interface A serial data interface (C-BUS) is used for command, status and data transfers between the CMX881 and the host C; this interface is compatible with microwire, SPI etc. Interrupt signals notify the host C when a change in status has occurred and the C should read the status register across the C-BUS and respond accordingly. Interrupts only occur if the appropriate mask bit has been set. See section 1.6.15. Auxiliary (Signal Monitor) analogue signal The CMX881 includes a Signal level monitor. This is an 8-bit successive approximation ADC and a two level signal sensor. The two level sensor facility can be used in conjunction with the power saving mode to wake up powered down blocks, and issue an interrupt on the IRQN line when the Signal exceeds the preset threshold level. The auxiliary ADC voltage reference is taken directly from the VDD(A) supply, so the Signal level being monitored should be derived from this supply voltage.
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1.5.1 Sleep Mode and Auto Start Up Power-on reset or C-BUS general reset places the CMX881 into sleep mode, which results in all internal blocks, except the xtal clock circuit, being placed in power-saved mode. The xtal clock circuit can be power-saved but this must be done by an explicit C-BUS command. Power saving is achieved by turning off bias current sources or disabling local clocks, as appropriate. During system standby periods, parts of the device can be put into sleep mode by the host to conserve power. The Auxiliary ADC can be programmed so that when the level exceeds a threshold, an interrupt is issued over the C-BUS and the selected mode (Tx or Rx) "woken up" within 400s. If this time is too long to ensure no part of the signal is lost, the DISC or MIC input and ADC path can be kept powered up whilst in standby mode. The receive modes and transmit modes can also be activated by commands from the C-BUS. On wake up, activation of the various signal path stages are phased appropriately to avoid causing unwanted transients. More details are provided in section 1.6.4 on Signal Routing. The CMX881 can be programmed to wake up its receive path automatically (automatic start-up) when the DISC input level exceeds the `high' level threshold. While the CMX881 is in automatic receive start-up mode the DISC input must also be selected for the signal path. When not in automatic start-up mode it is recommended that the required input is selected during Auxiliary ADC operation to avoid subsequent switching of the input signal source. 1.5.2 Auxiliary ADC This section of the CMX881 operates in both Tx and Rx modes and can be used to monitor one of 4 signal sources: Sig_Monitor pin, MIC1, Input_2 or DISC inputs. Activity on the selected input will optionally issue an interrupt if host intervention is required. During idle periods the majority of the CMX881 can be placed into low power mode. If monitoring ac signals connected to the Sig_Monitor pin they must be rectified and filtered using passive external circuitry. The Auxiliary ADC facility comprises an 8-bit ADC, a comparator, an 8-bit result data word and two 8-bit threshold registers, one defining the `Signal high' level and the other the `Signal low' level. The two threshold registers are combined into one 16-bit C-BUS register word. The ADC measures the Signal level at intervals that are set by C-BUS command. It is advised that the interval be set to <125s while waiting for a new incoming signal so that the CMX881 and host C can be powered up and put into the correct mode in time to avoid missing any part of the signal. The default interval period following a reset is 20.8s. Power dissipation of the Auxiliary ADC can be reduced by increasing the conversion interval time. The result of the most recent Auxiliary ADC measurement can be read over the C-BUS whenever the Signal Processing and Aux ADC circuits are powered up. The Auxiliary ADC compares each conversion result with the values in the `Signal high' or the `Signal low' threshold registers. The CMX881 can, for example, issue an interrupt to the host C to wake up the receive path when the Auxiliary ADC input exceeds the `high' level threshold. The CMX881 can also issue an interrupt to the host C to indicate a weak or absent signal when it falls below the `low' level threshold. This provides a user programmable hysteresis facility. The host must ensure that the value in the `low' register is always less than that of the `high' register. The options for issuing interrupts and for automatic start-up are selected by C-BUS command. The Auxiliary ADC options are controlled by the $B2, $B3 and $C0 C-BUS registers. The Auxiliary ADC requires the Auxiliary ADC, BIAS and Xtal clock to all be enabled in the Power Down Control register.
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1.5.3 Receive Mode The CMX881 can receive voice and various signal formats: CTCSS tone, DCS code, Selcall and FFSK/ MSK data at 1200 and 2400bps. Reception of each of these signal types can be independently enabled/disabled by C-BUS command. If enabled, an interrupt will be issued to notify the host C of the presence and type of the incoming signal. In receive mode the CMX881 performs signal type identification in 2 frequency bands, sub-audio (60 260Hz) and voice band (300 - 3kHz), to determine what type of signal is being received. When an enabled signal is detected this will be indicated to the host over the C-BUS and the CMX881 will continue to process the received signal in its band. Identification / process mode will continue in the other band. The CMX881 can process voice and simultaneously identify and process at least 2 other signal types (one in the sub-audio in parallel with one in the voice band). See Table 1 for valid combinations. The receive gain and audio output amplifier gain can be adjusted by the host C, via C-BUS command, to provide receive signal level adjustment and output volume control or muting. Table 1 Concurrent Rx Signalling Modes Supported by the CMX881 Sub-Audio All combinations of: With Rx Voice 1 Processing or Audio Tone generation DCS Inverted DCS CTCSS Sub-Audio All combinations of: No Voice Processing or Audio Tone generation DCS Inverted DCS CTCSS Voice band signalling Any one of A - E: A None B 1200bps FFSK/MSK C 2400bps FFSK/MSK D 1200 & 2400 bps FFSK/MSK E Selcall Voice band signalling All combinations of: Selcall 1200bps FFSK/MSK 2400bps FFSK/MSK
1 Including optional de-emphasis
By disabling all the decoding modes, the device can be configured to receive voice only signals with no decoding of the voice band, CTCSS or DCS signalling. This will result in reception of all signals as if they are voice. In this case it is up to the user/host C to respond appropriately to incoming signals. The CMX881 operates in half duplex, so whilst in receive mode the transmit path (microphone input and modulator output amplifiers) can be disabled and powered down if required. The AUDIO output signal level is equalised (to VBIAS) before switching between the audio port and the modulator ports, to minimise unwanted audible transients. The Off/Power-save level of the modulator outputs is the same as the VBIAS pin, so the audio output level must also be at this level before switching.
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1.5.3.1 Receiving Voice Band Signals When a voice based signal is being received, it is up to the C, in response to signal status information provided by the CMX881, to control muting/enabling of the voice band signal to the AUDIO output. The discriminator path through the device has a programmable gain stage. Whilst in receive mode this should normally be set to 0dB (the default) gain. Receive Filtering The incoming signal is filtered, as shown in Figure 5, to remove sub-audio components and to minimise high frequency noise. When appropriate the voice signal can then be routed to the AUDIO output.
10 250Hz 0 -10 Filter response -20 -30 -40 300Hz -50 -60 10Hz 100Hz 1000Hz Frequency (Hz) 10000Hz 100000Hz 3kHz Template
Figure 5 Rx Audio Filter Frequency Response De-emphasis Optional de-emphasis at -6dB per octave from 300Hz to 3000Hz (shown in Figure 6) can be selected to facilitate compliance with TIA/EIA-603.
16 12 8 4 dB 0 -4 -8
-3dB +1dB 0dB 0dB/octave -6dB/octave
-12 -16 -20 2500 250 100 1000 Frequency (Hz) 10000
-18dB/octave
Figure 6 De-emphasis Curve for TIA/EIA-603 Compliance
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1.5.3.2
Receiving and Decoding CTCSS Tones
The CMX881 is able to accurately detect valid CTCSS tones quickly to avoid losing the beginning of voice or possibly data transmissions, and is able to continuously monitor the detected tone with minimal probability of falsely dropping out. The received signal is filtered in accordance with the template shown in Figure 7, to prevent signals outside the sub-audio range from interfering with the sub-audio tone detection.
10 0 -10 Gain (dB) -20 -30 -40 -50 -60 -70 0 200 400 600 800 1000 Frequency (Hz)
Figure 7 Low Pass Sub-Audio Band Filter for CTCSS and DCS Once a valid CTCSS tone has been detected, the voice band signal can be passed to the audio output. The voice band signal is extracted from the received signal by band pass filtering as shown in Figure 5. To help decode received CTCSS tones adjustable decoder bandwidths and threshold levels permit decode certainty and signal to noise performance to be traded when congestion or range limits the system performance. This entails setting the tone decoder bandwidth and threshold level in P2.1 of the Programming register ($C8) and programming the Audio & CTCSS Control register with the desired tone. Tone Cloning: TM Tone Cloning facilitates the detection of CTCSS tones 1 to 39 in receive mode. This allows the device to non-predictively detect any tone in this range. The received tone number will be reported in the Tones Status register. This tone code can then be programmed into the `Audio and Device Address Control' register, by the host C. The cloned tone will only be active when CTCSS is enabled in the Mode register.
Tone Cloning is a trademark of CML Microsystems Plc.
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CTCSS Tones Table 2 lists the CTCSS tones available. The tone numbers are decimal equivalents of the numbers written to the Audio & CTCSS Control register ($C2) and reported in the Tone Status register ($CC). Table 2 CTCSS Tones Tone Number 1 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 Notes: 1 Freq. (Hz) No Tone 67.0 71.9 74.4 77.0 79.7 82.5 85.4 88.5 91.5 94.8 97.4 100.0 103.5 107.2 110.9 114.8 118.8 123.0 127.3 Tone Number 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Freq. (Hz) 131.8 136.5 141.3 146.2 151.4 156.7 162.2 167.9 173.8 179.9 186.2 192.8 203.5 210.7 218.1 225.7 233.6 241.8 250.3 69.3 Tone Number 40-54 552 >=56 Freq. (Hz) Reserved Invalid tone Reserved
Tone number 00 in the Tone Status register ($CC) indicates that none of the above subaudio tones is being detected - see also section 1.6.19. If tone number 00 is programmed into the Audio & CTCSS Control register ($C2) no tone will be scanned for. If CTCSS transmit is selected this tone setting will cause the CTCSS generator to output no signal. Tone number 55 is reported in the Tone Status register ($CC), when CTCSS receive is enabled and a subaudio tone is detected that does not correspond to the selected tone. This could be a tone in the subaudio band which is not in the table or a tone in the table which is not the selected tone.
2
1.5.3.3 Receiving and Decoding DCS Codes DCS Code is in NRZ format and transmitted at 134.4 0.4bps. The CMX881 is able to decode any 23 or 24 bit pattern in either of the two DCS modulation modes defined by TIA/EIA-603 and described in Table 3. The CMX881 can detect a valid DCS Code quickly enough to avoid losing the beginning of voice transmissions. Table 3 DCS Modulation Modes Modulation Type: A B Data Bit: 0 1 0 1 FM Frequency Change: Minus frequency shift Plus frequency shift Plus frequency shift Minus frequency shift
The CMX881 detects the DCS code that matches the programmed code defined in the `DCS Code' words (P2.2-3) in the Programming register ($C8). To detect the pre-programmed DCS code the signal is low pass filtered to suppress all but the sub-audio band using the filter shown in Figure 7. Further equalisation filtering, signal slicing and level detection are done to extract the code being received. The extracted code is then matched with the programmed 23 or 24-bit DCS code to be recognised, in the order least significant first through to most significant DCS
2004 CML Microsystems Plc 18 D/881/7
PMR Signalling Processor
CMX881
code bit last. Table 4 shows a selection of valid 23-bit DCS codes, this does not preclude other codes being programmed. Recognition of a valid DCS Code will be flagged if the decode is successful (3 or less errors). A failure to decode is indicated by a '0' flag. This flag is updated after the decoding of every 4th bit of the incoming signal. Once a valid DCS Code has been detected, the voice band signal can be passed to the AUDIO output under the control of the host C. The voice signal is extracted from the received input signal by band pass filtering; see Figure 5. More details for programming DCS Codes are provided in section 1.6.20.3. The end of DCS transmissions is indicated by a 134.4 0.5Hz tone for 150-200ms. To detect the DCS turn off tone while receiving DCS, the DCS turn off tone option must be selected in the Audio and CTCSS Control ($C2) register, and, CTCSS receive must also be enabled. When a DCS turn off tone is detected it will cause a DCS interrupt; the receiver audio output can then be muted by the host. Table 4 DCS 23 Bit Codes DCS Code 023 025 026 031 032 043 047 051 054 065 071 072 073 074 114 115 116 125 131 132 134 143 152 155 156 162 165 172 DCS bits 22-12 763 6B7 65D 51F 5F5 5B6 0FD 7CA 6F4 5D1 679 693 2E6 747 35E 72B 7C1 07B 3D3 339 2ED 37A 1EC 44D 4A7 6BC 31D 05F DCS bits 11-0 813 815 816 819 81A 823 827 829 82C 835 839 83A 83B 83C 84C 84D 84E 855 859 85A 85C 863 86A 86D 86E 872 875 87A DCS Code 174 205 223 226 243 244 245 251 261 263 265 271 306 311 315 331 343 346 351 364 365 371 411 412 413 423 431 432 DCS bits 22-12 18B 6E9 68E 7B0 45B 1FA 58F 627 177 5E8 43C 794 0CF 38D 6C6 23E 297 3A9 0EB 685 2F0 158 776 79C 3E9 4B9 6C5 62F DCS bits 11-0 87C 885 893 896 8A3 8A4 8A5 8A9 8B1 8B3 8B5 8B9 8C6 8C9 8CD 8D9 8E3 8E6 8E9 8F4 8F5 8F9 909 90A 90B 913 919 91A DCS Code 445 464 465 466 503 506 516 532 546 565 606 612 624 627 631 632 654 662 664 703 712 723 731 732 734 743 754 DCS bits 22-12 7B8 27E 60B 6E1 3C6 2F8 41B 0E3 19E 0C7 5D9 671 0F5 01F 728 7C2 4C3 247 393 22B 0BD 398 1E4 10E 0DA 14D 20F DCS bits 11-0 925 934 935 936 943 946 94E 95A 966 975 986 98A 994 997 999 99A 9AC 9B2 9B4 9C3 9CA 9D3 9D9 9DA 9DC 9E3 9EC
1.5.3.4 Receiving and Decoding Selcall Tones Selcall tones can be used to flag the start and end of a call. They may also occur during a call in which case the tone may be audible at the receiver. If enabled, an interrupt will be issued when a signal matching a valid Selcall tone is detected and when a present Selcall tone turns off or changes (i.e. at the start and at the end of each Selcall tone). The audio path can then be turned on and off at the appropriate times under control of the host C. The CMX881 implements a fully programmable Selcall encoder / decoder. The frequency of each tone is defined in the Program registers P1.2-18. See section 1.6.20 for programming details. In receive the CMX881 scans through the tone table sequentially, the code reported will be the first one that matches the incoming frequency.
2004 CML Microsystems Plc 19 D/881/7
PMR Signalling Processor
CMX881
Adjustable decoder bandwidths, threshold levels are programmable via the Programming register and permits certainty of detection and signal to noise performance to be traded when congestion or range limits the system performance. The Selcall signal is derived from the received input signal after the band pass filtering shown in Figure 5. Table 5 lists the Selcall codes available, these are 5 bit numbers set or reported in: Tx Tone register ($C3) and Tone Status register ($CC). Table 5 Selcall Tones Special / Information Tones th (5 bit = 0) 4 bit Code Frequency set in Dec Hex Program register: 0 0 No Tone 1 1 2 2 3 3 4 4 5 5 6 6 1-13 7 7 Reserved 8 8 9 9 10 A 11 B 12 C 13 D 1,2 14 E P1.2 15 F Reserved Notes: 1 Normal Tones (5th bit = 1) 4 bit Code Frequency set in Dec Hex Program register: 1 0 0 P1.3 1 1 1 P1.4 1 2 2 P1.5 1 3 3 P1.6 1 4 4 P1.7 1 5 5 P1.8 1 6 6 P1.9 1 7 7 P1.10 1 8 8 P1.11 1 9 9 P1.12 1 10 A P1.13 1 11 B P1.14 1 12 C P1.15 1 13 D P1.16 1 14 E P1.17 1 15 F P1.18
Special tone 14, and Normal tones 0 - 15 provide user programmable tone options for both transmit and receive modes as set in the indicated Program register, for programming information see section 1.6.20.2. To ensure correct operation tones should not be programmed with overlapping detect bandwidths. Special tone 14 is the repeat tone, this code must be used in transmit when the new code to be sent is the same as the previous one. e.g. to send `333' the sequence `3R3' should be sent, where `R' is the repeat tone. When receiving Selcall tones the CMX881 will indicate the repeat tone when it is received, it is up to the host to interpret this and decode tones accordingly.
2
2004 CML Microsystems Plc
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D/881/7
PMR Signalling Processor
CMX881
1.5.3.5 Receiving FFSK Signals The CMX881 can decode incoming FFSK/MSK signals at either 1200 or 2400 baud data rates. It can achieve this by deriving the baud rate from the received signal. Alternatively a control word may set the baud rate, in which case the device only responds to signals operating at that rate. The form of FFSK/MSK signals for these baud rates, excluding noise, is shown in Figure 11. The received signal is filtered and data is extracted. A PLL is used to extract the clock from the recovered serial data stream. The recovered data is stored in a 1 byte buffer and an interrupt issued to indicate received data is ready. Data is transferred over the C-BUS, controlled by host instructions. If this data is not read before the next data is decoded it will be overwritten. The MSK bit clock is not output externally. It is up to the user to ensure that the data is transferred at an adequate rate following data ready being flagged, see Table 9. The extracted data is compared with up to three 16-bit programmed frame sync patterns (SYND, SYNC and it's inverse SYNT). SYNC and SYND are both preset to $C4D7 following a RESET command. An interrupt will be flagged when the programmed frame sync pattern is detected. The host may stop the frame sync search by disabling the MSK demodulator. FFSK may be transmitted in conjunction with a CTCSS or DCS sub-audio component. The device will handle the sub-audio signals as already described. If a sub-audio signal turns off during reception of FFSK, it is up to the host C to turn off the FFSK decoding as the device will continue receiving and processing the incoming signal until commanded otherwise by the host C. The host must keep track of the message length or otherwise determine the end of reception (e.g. by using sub-audio information or the Auxiliary ADC to check for signal level) and disable the FFSK demodulator at the appropriate time.
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D/881/7
PMR Signalling Processor
CMX881
1.5.4 Transmit Mode The device operates in half duplex, so when the device is in transmit mode the receive path (discriminator and audio output amplifiers) should be disabled, and can be powered down, by the host C. Two modulator outputs with independently programmable gains are provided to facilitate single or twopoint modulation, separate sub-audio and voice band outputs. If one of the modulator outputs is not used it can be disabled to conserve power. To avoid erroneous transmission of out of band frequencies when changing from Rx to Tx the MOD_1 and MOD_2 outputs are ramped to the quiescent modulator output level, VBIAS before switching. Similarly, when starting a transmission, the transmitted signal strength is ramped up from the quiescent VBIAS level and when ending a transmission the transmitted signal strength is ramped down to the quiescent VBIAS level. The ramp rates are set in the Programming register P4.6. When the modulator outputs are disabled, their outputs will be set to VBIAS. When the modulator output drivers are powered down, their outputs will be floating (high impedance), so the RF modulator will need to be turned off. Table 6 Concurrent Tx Modes Supported by the CMX881 Sub-Audio CTCSS CTCSS CTCSS CTCSS CTCSS DCS DCS DCS DCS DCS + + + + + + + + Voice band Voice Selcall FFSK/MSK DTMF Voice Selcall DTMF FFSK/MSK Voice Selcall DTMF FFSK/MSK
For all transmissions the host must only enable signals after the appropriate data and settings for those signals are loaded into the C-BUS registers. As soon as any signalling is enabled the CMX881 will use the settings to control the way information is transmitted. A programmable gain stage in the microphone input path facilitates a host controlled VOGAD capability.
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D/881/7
PMR Signalling Processor
CMX881
1.5.4.1 Processing Voice Signals for Transmission over Analogue Channels The microphone input(s), with programmable gain, can be selected as the voice input source. Preemphasis is selectable with either version of the 2 analogue Tx audio filters (for 12.5kHz and 25kHz channel spacing). These are designed for use in ETS-300-086 and/or TIA/EIA-603 compliant applications. Both filters attenuate sub-audio frequencies below 250Hz by more than 33dB wrt the signal level at 1kHz. These filters together with a built in limiter help ensure compliance with ETS-300-086 (25kHz and 12.5kHz channel spacing) when levels and gain settings are set up correctly in the target system.
10 0 -10 Gain (dB) -20 -30
-33dB -14dB/octave +0.5dB/-2dB wrt ref. reference 0dB at 1kHz 3kHz
250Hz
-40 -50 -60 10 100 1000 Frequency (Hz) 10000 100000
Figure 8 25kHz Channel Audio Filter Response Template The filter characteristics of the 12.5kHz channel filter fits the filter template shown in Figure 9 (solid outline). This filter also facilitates implementation of systems compliant with TIA/EIA-603 `A' and `B' bands. To achieve attenuation above 3kHz of better than -100dB/decade for TIA/EIA-603 `C' bands (dashed outline), additional external circuitry is required, such as suggested in section 1.4.2.
10 0 -10
250Hz 300Hz +0.5dB/-2dB wrt ref. reference 0dB at 1kHz 3kHz
-20 Gain (dB) -30 -40 -50 -60 -70 -80 -90 10 100
-33dB
300Hz
-60dB/decade wrt ref. 2.55kHz
(-50dB) 20kHz -100dB/decade
(-82.5dB) 20kHz
1000 Frequency (Hz)
10000
100000
Figure 9 12.5kHz Channel Audio Filter Response Template
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D/881/7
PMR Signalling Processor
CMX881
The CMX881 provides selectable pre-emphasis filtering of +6dB per octave from 300Hz to 3000Hz, matching the template shown in Figure 10.
16 12 8 4 dB 0 -4 -8 -12 -16 -20 2500 250 100 1000 Frequency (Hz) 10000
+12dB/octave -3dB +1dB 0dB +6dB/octave
Figure 10 Audio Frequency Pre-emphasis Template Modulator Output Routing The sub-audio component can be combined with the voice band signal and this composite signal routed to both MOD_1 and MOD_2 outputs, or the sub-audio and voice band signal can be output separately (sub-audio to MOD_2 and voice band to MOD_1), in accordance with the settings of the Signal Routing register ($B1). 1.5.4.2 CTCSS Tone The sub-audio CTCSS tone generated is defined in the Tx CTCSS register ($C2). Table 2 lists the CTCSS tones and the corresponding value for programming the TX TONE bits. 1.5.4.3 DCS Code A 23 or 24-bit sub-audio DCS Code can be generated, as defined by the `DCS Code' words (P2.4-5) of the Programming register ($C8); the same DCS Code pattern is used for detection and transmission. The DCS Code is NRZ encoded at 134.40.4 bits/s, low pass filtered and added to the voice band signal, prior to passing the signal to the modulator output stages. Valid 23-bit DCS codes and the corresponding settings for the DCS Code Register are shown in Table 4, this does not preclude other codes being programmed. The least significant bit of the DCS code is transmitted first and the most significant bit is transmitted last. The CMX881 is able to encode and transmit either of the two DCS modulation modes defined by TIA/EIA-603 and described in Table 3. To signal the end of the DCS transmission, the host should set the special sub-audio bits in the Audio & CTCSS Control register ($C2) to enable the DCS turn off tone for 150ms to 200ms. After this time period has elapsed the host should then disable DCS in the Mode register ($C1). Do not enable CTCSS in the Mode Control ($C1) register when transmitting the DCS turn off tone. To summarize, detection of DCS turn off tone requires the CTCSS decoder to be enabled, whereas generation of the DCS turn off tone requires the CTCSS encoder to be disabled.
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D/881/7
PMR Signalling Processor
CMX881
1.5.4.4 Transmitting Selcall Tones The Selcall tone to be generated is defined in the Tx Tone register ($C3). The tone level is set in the Programming register (P1.0). The Selcall tone must be transmitted without other signals in the voice band, so the host C must disable the voice path prior to initiating transmission of a Selcall tone, and restore the voice path after the Selcall tone transmission is complete. Table 5 shows valid Selcall tones, together with the values for programming the Selcall bits of the Tx Tone register. Custom Selcall tone frequencies are set in the program register ($C8) P1.2-18. See section 1.6.20.2 for programming details. 1.5.4.5 Transmitting FFSK/MSK Signals The FFSK/MSK encoding operates in accordance with the bit settings in the Mode Control register ($C1). When enabled the MSK modulator will immediately begin transmitting data using the settings and values in the Tx Data and General Control register(s) and block 0 of the Programming Register. Therefore, these registers should be programmed to the required value before transmission is enabled. The CMX881 generates it's own internal data clock and converts the binary data into the appropriately phased frequencies, as shown in Figure 11 and Table 7. The binary data is taken from register $CA, most significant bit first. The following data words must be provided over the C-BUS within certain time limits to ensure the selected baud rate is maintained. The time limits will be dependent on the data coding being used, see Table 9.
Rx SIGNAL I/P 2400 BAUD
LOGIC '1'
LOGIC '0'
LOGIC '1'
LOGIC '0'
Rx SIGNAL I/ P 1200 BAUD
LOGIC '1'
LOGIC '0'
LOGIC '1'
LOGIC '0'
Figure 11 Modulating Waveforms for 1200 and 2400 Baud FFSK/MSK Signals The table below shows the combinations of frequencies and number of cycles to represent each bit of data, for both baud rates. Table 7 Data Frequencies for each Baud Rate Baud Rate 1200 baud 2400 baud Data 1 0 1 0 Frequency 1200Hz 1800Hz 1200Hz 2400Hz Number of Cycles one one and a half half one
Note: FFSK may be transmitted in conjunction with a CTCSS or DCS sub-audio component.
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D/881/7
PMR Signalling Processor
CMX881
1.5.4.6 Transmitting DTMF Tones The DTMF signals to be generated are defined in the TX TONE register ($C3). Single tones and twist (lower frequency tone reduced by 2dB) can be enabled by setting the appropriate bit in the $C3 register to '1'. The DTMF level is set in programming register P1.0. The DTMF tones must be transmitted on their own within the voice band, the host C must disable other voice band signals prior to initiating transmission of the DTMF tones, and (if required) restore the voice band signals after the DTMF transmission is complete. Table 8 shows the DTMF tone pairs, together with the values for programming the `Tone Pair' field of the TX TONE register. Table 8 DTMF Tone Pairs and Corresponding Tx Programming Codes Tone Pair Code (Hex) 1 2 3 4 5 6 7 8 9 A B C D E F 0 Key Pad Position 1 2 3 4 5 6 7 8 9 0 * # A B C D Low Tone (Hz) 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 High Tone (Hz) 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633
Note: Only the underlined tone is generated when the 'Single Tone' bit is enabled. 1.5.5 FFSK/MSK Data packeting The CMX881 has a built in 15 bit CRC and 1 bit parity generator / checker to ease host processing during transmission and reception of data packets. The CRC / parity function can be used with any length message in both Tx and Rx modes. In Tx the host may reset, add to or send the 2 byte checksum at any byte boundary in the data sequence. In Rx the host may reset the checking circuit at any byte boundary and the CMX881 will indicate for each subsequent byte if the preceding bytes satisfied the CRC and parity requirements. Tx frame example:
Write Mode reg 2 MSK transfer flag Read Status reg 2 Write Tx Data reg 2 Enable CRC bit Tx CRC bit
1 1
BS
BS
FS
FS
0
1
2
3
0
1
2
...
Tx over air data
BS
BS
FS
FS
0
1
2
3
CS
CS
0
1
2
...
BS = Bit sync Notes:
FS = Frame sync
0, 1, ... Data bytes
CS = Checksum
1 The Tx CRC and Enable CRC bits are controlled by writing to the Tx Data register 2 Actions requiring a C-BUS transfer
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D/881/7
PMR Signalling Processor
CMX881
Rx frame example:
Rx over air data Write Mode reg
2
BS
BS
FS
FS
0
1
2
3
CS
CS
0
1
2
...
Frame Sync flag MSK transfer flag Read Status reg 2 Checksum bit
3
Read Rx Data reg 2 Enable CRC bit
2,1
0
1
2
3
CS
CS
0
1
2
BS = Bit sync Notes:
FS = Frame sync
0, 1, ... Data bytes
CS = Checksum
1 The Enable CRC bit is controlled by writing to the Tx Data register 2 Actions requiring a C-BUS transfer 3 The Checksum bit is read from the Rx Data register
1.5.5.1 Tx Hang bit When transmitting FFSK/MSK data, the user should ensure that the data is terminated with a hang bit. This is recommended regardless of whether the on-chip data formatting is used. To do this, the host must set the 'Last Data' bit in the Tx Data register ($CA) when the message is required to end. This will append a hang bit onto the end of the current byte and generate (if enabled) an interrupt when the last Tx data has left the modulator.
Write Mode reg 2 MSK transfer flag Tx MSK end flag Read Status reg 2 Write Tx Data reg 2 Enable CRC bit Tx CRC bit Last Data bit
1 1 1
BS
BS
FS
FS
0
1
2
3
Tx over air data
BS
BS
FS
FS
0
1
2
3
CS
CS
H
BS = Bit sync
FS = Frame sync
0, 1, ... Data bytes
CS = Checksum
H = Hang Bit
Notes: 1 The Tx CRC, Enable CRC and Last Data bits are changed by writing to the Tx Data register 2 Actions requiring a C-BUS transfer 1.5.5.2 Data Buffer Timing Data must be transferred at the rate appropriate to the signal type and data format. The CMX881 buffers signal data in the lower 8-bits of a 16-bit register. The CMX881 will issue interrupts to indicate when data is available or required. The host must respond to these interrupts within the maximum allowable latency for the signal type. Table 9 shows the maximum latencies for transferring signal data to maintain appropriate data throughput. Table 9 Maximum Data Transfer Latency Data type 1200b/s MSK 2400b/s MSK Max time to read from or write to data buffer 6.6ms 3.3ms Data buffer size 8 bits 8 bits
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D/881/7
PMR Signalling Processor
CMX881
1.5.6 C-BUS Operation This block provides for the transfer of data and control or status information between the CMX881's internal registers and the C over the C-BUS serial interface. Each transaction consists of a single Register Address byte sent from the C which may be followed by one or more data byte(s) sent from the C to be written into one of the CMX881's Write Only Registers, or one or more data byte(s) read out from one of the CMX881's Read Only Registers, as illustrated in Figure 12. Data sent from the C on the Command Data line is clocked into the CMX881 on the rising edge of the Serial_Clock input. Reply Data sent from the CMX881 to the C is valid when the Serial_Clock is high. The CSN line must be held low during a data transfer and kept high between transfers. The C-BUS interface is compatible with most common C serial interfaces and may also be easily implemented with general purpose C I/O pins controlled by a simple software routine. The number of data bytes following an A/C byte is dependent on the value of the A/C byte. The most significant bit of the address or data are sent first. For detailed timings see section 1.8.1.
C-BUS Write: See Note 1 CSN Serial_Clock CMD_DATA 7
MSB
See Note 2
6
5
4
3
2
1
0
LSB
7
MSB
6
...
0
LSB
7
MSB
...
0
LSB
Address / Command byte REPLY_DATA
High Z state
Upper 8 bits
Lower 8 bits
C-BUS Read: See Note 2 CSN Serial_Clock CMD_DATA 7
MSB
6
5
4
3
2
1
0
LSB
Address byte REPLY_DATA
High Z state
Upper 8 bits 7
MSB
Lower 8 bits 7
MSB
6
...
0
LSB
...
0
LSB
Data value unimportant
Repeated cycles
Either logic level valid
Figure 12 C-BUS Transactions Notes: 1. For Command byte transfers only the first 8 bits are transferred ($01 = Reset). 2. For single byte data transfers only the first 8 bits of the data are transferred. 3. The CMD_DATA and REPLY_DATA lines are never active at the same time. The Address byte determines the data direction for each C-BUS transfer. 4. The Serial_Clock input can be high or low at the start and end of each C-BUS transaction. 5. The gaps shown between each byte on the CMD_DATA and REPLY_DATA lines in the above diagram are optional, the host may insert gaps or concatenate the data as required.
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D/881/7
PMR Signalling Processor
CMX881
1.6
1.6.1
C-BUS Register Description
C-BUS Register Summary
C-BUS Write Only Registers ADDR. (hex) $01 $B0 $B1 $B2 $B3 $C0 $C1 $C2 $C3 $C7 $C8 $CA $CB $CD $CE $CF REGISTER C-BUS RESET ANALOGUE GAIN SIGNAL ROUTING AUXILIARY ADC THRESHOLDS AUXILIARY ADC CONTROL POWER DOWN CONTROL MODE CONTROL AUDIO & CTCSS CONTROL TX TONE RESERVED REGISTER ADDRESS PROGRAMMING REGISTER TX DATA RESERVED REGISTER ADDRESS AUDIO TONE INTERRUPT MASK RESERVED REGISTER ADDRESS Word Size (bits) 0 16 16 16 8 16 16 16 16 16 16 16 16 16 16 16
The C-BUS addresses $C7, $CB and $CF are allocated for production testing and must not be accessed in normal operation. C-BUS Read Only Registers ADDR (hex) $B4 $C5 $C6 $C9 $CC Interrupt Operation The CMX881 will issue an interrupt on the IRQN line when the IRQ bit (bit 15) of the Status register and the IRQ Mask bit (bit 15) are both set to `1'. The IRQ bit is set when the state of the interrupt flag bits in the Status register change from a '0' to a '1' and the corresponding mask bit(s) in the Interrupt Mask register is(are) set. All interrupt flag bits in the Status register except the Programming Flag (bit 0) are cleared and the interrupt request is cleared following the command/address phase of a C-BUS read of the flag register. The Programming Flag bit is set to '1' only when it is permissible to write a new word to the Programming register. REGISTER AUXILIARY ADC DATA RX DATA STATUS RESERVED REGISTER ADDRESS TONE STATUS Word Size (bits) 8 16 16 16 16
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D/881/7
PMR Signalling Processor
CMX881
1.6.2
$01 C-BUS RESET: address only.
The reset command has no data attached to it. It sets the device registers into the states listed below. Addr. $B0 $B1 $B2 $B3 $B4 $C0 $C1 $C2 $C3 $C5 $C6 $C7 $C8 $CA $CC $CD $CE $CF REG. ANALOGUE GAIN SIGNAL ROUTING AUXILIARY ADC THRESHOLDS AUXILIARY ADC TIMING AUXILIARY ADC DATA POWER DOWN CONTROL MODE CONTROL AUDIO & CTCSS CONTROL TX TONE RX DATA STATUS Reserved Register Address PROGRAMMING REGISTER TX DATA TONE STATUS AUDIO TONE INTERRUPT MASK Reserved Register Address 15 14 13 12 11 10 9 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 8 0 0 1 7 0 0 0 0 X 0 0 0 0 X 0 0 0 0 0 0 0 0 6 0 0 0 0 X 0 0 0 0 X 0 0 0 0 0 0 0 0 5 0 0 0 0 X 0 0 0 0 X 0 0 0 0 0 0 0 0 4 0 0 0 0 X 0 0 0 0 X 0 0 0 0 0 0 0 0 3 0 0 0 2 0 0 0 1 0 0 0 0 X 0 0 0 0 X 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 0 X 0 0 0 0 0 0 0 0
00 00 00 00 XX 00 00 00 00 00 00 00 00
0 0 0 0 X 0 0 0 0 0 0 0 0
0 0 0 0 X 0 0 0 0 0 0 0 0
0 0 0 0 X 0 0 0 0 0 0 0 0
0 0 0 0 X 0 0 0 0 0 0 0 0
00 00 00 00 XX 00 00 00 00 00 00 00 00
00 XX 00 00 00 00 XX 00 00 00 00 00 00 00 00
Following a C-BUS reset all of the programming registers (P0 - P4) are reset to zero except the following: P0.0 P0.1 P0.2 P0.3 P4.7 Frame SYNC LSB Frame SYNC MSB Frame SYND LSB Frame SYND MSB Transmit Limiter Control 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 1 0 1 1 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 0 -
This initiates the device with the MPT frame SYNC pattern of $C4D7 and the PAA frame SYND pattern of $B433. The transmit limiter value is initialised to the maximum limit.
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D/881/7
PMR Signalling Processor
CMX881
1.6.3 Bit:
$B0 ANALOGUE GAIN: 16-bit write-only
15 Inv_1 14 13 MOD_1 Attenuation 12 11 Inv_2 10 9 MOD_2 Attenuation 8 7 0 6 5 Input Gain 4 3 2 1 0 Audio Output Attenuation
Bits 15 and 11 set the phase of the MOD_1 and MOD_2 outputs. When set to '0' the 'true' signal (0 phase shift) will be produced, when set to '1' the signal will be inverted (180 phase shift). This can be useful when interfacing with rf circuitry or when generating an inverted turn off tone for CTCSS. Any change will take place immediately after these bits are changed. The output paths provide user programmable attenuation stages to independently adjust the output levels of the modulators. Finer level control of the MOD_1 and MOD_2 outputs can be achieved with the FINE OUTPUT GAIN 1 and FINE OUTPUT GAIN 2 registers (P4.2-3). Bit 14 Bit 13 Bit 12 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 MOD_1 Output Attenuation >40dB 12dB 10dB 8dB 6dB 4dB 2dB 0dB Bit 10 0 0 0 0 1 1 1 1 Bit 9 0 0 1 1 0 0 1 1 Bit 8 0 1 0 1 0 1 0 1 MOD_2 Output Attenuation >40dB 12dB 10dB 8dB 6dB 4dB 2dB 0dB
Bit 7 is reserved - set to 0. Bits 6 to 4 control the input path programmable gain stage - useful when amplifying low power voice signals from the microphone inputs. Finer gain control can be achieved with the `FINE INPUT GAIN' control register (P4.0). In receive mode it is recommended to set the gain to 0dB. Bit 6 0 0 0 0 1 1 1 1 Bit 5 0 0 1 1 0 0 1 1 Bit 4 0 1 0 1 0 1 0 1 Input Gain 0dB 3.2dB 6.4dB 9.6dB 12.8dB 16.0dB 19.2dB 22.4dB Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Audio Output Attenuation >60dB 44.8dB 41.6dB 38.4dB 35.2dB 32.0dB 28.8dB 25.6dB 22.4dB 19.2dB 16.0dB 12.8dB 9.6dB 6.4dB 3.2dB 0dB
Bits 3 to 0 control the output path programmable attenuation stage to adjust the volume of the audio output signal. Finer volume control can be achieved with the `FINE OUTPUT GAIN 1' control register (P4.2).
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31
D/881/7
PMR Signalling Processor
CMX881
1.6.4 Bit:
$B1 SIGNAL ROUTING: 16-bit write-only
15 0 14 0 13 12 11 0 10 0 9 0 8 0 7 0 6 0 5 4 3 2 1 Ramp Up 0 Ramp Down Tx MOD_1 and MOD_2 Routing Analogue i/p select AUDIO o/p select
Bits 15 and 14 reserved - set to 0. Bits 13 and 12 select the routing of the transmit signals allowing 1 or 2 point modulation and interfaces. Bit 13 0 0 1 1 Bit 12 0 1 0 1 Tx MOD_1 and MOD_2 routing Tx, MOD_1 and MOD_2 outputs set to bias. Tx, In band signals to MOD_1, Subaudio signals to MOD_2 Tx, In band and Subaudio to MOD_1, MOD_2 set to bias Tx, In band and Subaudio to both MOD_1 and MOD_2
`In-Band' in this context refers to any of the signals; Voice, Selcall tone, DTMF etc. Bits 11 to 6 are reserved - set to 0. Bit 5 0 0 1 1 Bit 3 0 0 1 1 Bit 4 0 1 0 1 Bit 2 0 1 0 1 Analogue Input select No input selected (Input = VBIAS) Input amplifier 2 (Input_2 i/p) Microphone (MIC i/p) Discriminator (DISC i/p) AUDIO Output select No output selected (Output = VBIAS) Received Voice signal MOD_1 signal (for Tx monitoring) Reserved, do not use
When bits 1 or 0 are set to '1' output signals are ramped up (bit 1) or ramped down (bit 0) to reduce transients in the transmitted signal. Time to ramp up / down is set in the 'Ramp Rate Control' section of the Programming register (P4.6). 1.6.5 Bit: $B2 AUXILIARY ADC THRESHOLDS: 16-bit write-only
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 High Threshold [Range: 0 to 255] Low Threshold [Range: 0 to 255]
If the selected signal level exceeds the High Threshold, the `Signal High' bit of the Status register will be set to 1. If the Signal level falls below the Low Threshold, the `Signal Low' bit of the Status register will be set to 1. If the corresponding interrupt bit is enabled, a C-BUS interrupt will be generated. These status bits are cleared when the Status register is read. The behaviour of the CMX881 is not defined if the high threshold is less than the low threshold. Threshold resolution: Threshold accuracy: Differential linearity: VDD(A)/256 per LSB 2 LSB 1 LSB [monotonic]
The `Auxiliary ADC Thresholds' register must not be updated whilst the Auxiliary ADC is enabled.
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D/881/7
PMR Signalling Processor
CMX881
1.6.6 Bit:
$B3 AUXILIARY ADC CONTROL: 8-bit write-only
7 6 5 4 3 2 1 0 Aux ADC i/p select Conversion Interval
The `Conversion Interval' (bits 5 to 0) defines the time between measurements whilst the Auxiliary ADC is enabled. This allows the user to trade-off device power consumption with response time. (approximate) = 0.5mW/VDD(A)/conversion (approximate) = 20.8s per LSB. The user should set an interval to ensure that no part of a received signal is missed, so that the signal type can be correctly identified. If using the Rx Auto start-up feature the recommended maximum Conversion Interval is 125s. The `Auxiliary ADC' register must not be updated whilst the Aux ADC is enabled. Auxiliary ADC power Conversion Interval The Aux ADC i/p select (bits 7 to 6) control the input to the Auxiliary ADC. Control is independent of the Analogue i/p select bits and hence the Aux ADC can monitor any one of the 4 inputs independently. Bit 7 0 0 1 1 1.6.7 Bit: Bit 6 0 1 0 1 Auxiliary ADC input from: Signal monitor (Sig_Monitor i/p) Input amplifier 2 (Input_2 i/p) Microphone (MIC i/p) Discriminator (DISC i/p)
$C0 POWER DOWN CONTROL: 16-bit write-only
15 Input_2 amp 14 MIC amp 6 BIAS 13 Disc amp 5 Signal Processing 12 Input Gain 4 Prog Reg Save 11 Output Fine Gain 1 3 Xtal_N 10 Output Fine Gain 2 2 Clock_Out_N 9 O/P Coarse Gain 1 1 Enable Aux ADC 8 O/P Coarse Gain 2 0 Rx Auto start-up
Bit:
7 Audio Output
Bits 15 to 5 provide the power control of the specified blocks. If a bit is '1', the corresponding block is on, else it is powered down. A C-BUS or Power up reset clears all bits in this register to '0'. If bit 5 is '0' the internal signal processing blocks are reset and placed into a power-save mode. Bit 4 should be set to a '1' if any of the program registers (1.6.20) have been programmed as this prevents them being reset after a Rx Auto start-up or when the Signal Processing blocks come out of power save. If bit 4 is set to '0' the program registers will be reset to the C-BUS or Power-up reset state whenever the Signal Processing blocks come out of power save. Bits 3 and 2 control the xtal clock circuit. The xtal circuit is powered down by setting bit 3 to '1'. Note: The Clock/Xtal pin may be driven by an external clock source regardless of the setting of these bits. The Clock_Out pin is disabled (held low) by setting bit 2 to `1'. After a Power-up or C-BUS reset bits 2 and 3 are cleared to `0', so that both the xtal circuit and clock output are enabled. Bit 1 controls the Auxiliary ADC. If set to '1' the Auxiliary ADC will generate interrupts in accordance with the settings of the interrupt mask bits. If bit 1 is '0' the Auxiliary ADC is disabled and powered down. Bit 0 controls Rx Auto start up. If bit 0 is set to '1' and the Aux ADC input rises above the `High Threshold' the device will automatically enter receive mode and initiate Rx signal type identification for those signals enabled in the Mode register. The correct Aux ADC input, Rx signal routing and power down bits must be set for automatic receive start up to operate, the mode control bits should be set to '00' in this case. If bit 0 is cleared to '0' the CMX881 will not automatically start-up and it is up to the host to respond to Aux ADC interrupts in this case. Bit 0 must be set to '0' whilst writing through register $C8 Programming Register.
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33
D/881/7
PMR Signalling Processor
CMX881
1.6.8 Bit:
$C1 MODE CONTROL: 16-bit write-only
15 Enable Voice 14 13 12 Generate Audio Tone 4 Enable 2400b/s 11 Enable CTCSS 3 Enable 1200b/s 10 Enable DCS 9 Enable DCS Inverse 1 Mode Select 8 0 In band signalling: Selcall, Tx DTMF 6 SYND 5 SYNT
Bit:
7 SYNC
2 0
0
Bits 1 and 0 control the overall mode of the CMX881 according to the table below: Bit 1 0 0 1 1 Bit 0 0 1 0 1 Device Mode Idle Receive Mode Transmit Mode Reserved - do not use
During transmit, only one signal type may be enabled for each of the sub-audio and voice bands, see Table 8. During receive the CMX881 will search for all signals enabled in this register and report those that are successfully decoded. See also Table 1 in section 1.5.3. In transmit mode the CMX881 begins transmission of a selected signal immediately after it has been enabled. The host C must ensure all associated data and control bits have been set to their required values before enabling the signal in this register. Bits 4 and 3 control the modem functions of the CMX881 in accordance with the following table: Bit 4 0 0 1 1 Bit 3 0 1 0 1 Tx - Transmitted signal None MSK 1k2b/s MSK 2k4b/s Reserved Rx - Monitored signal(s) None MSK 1k2b/s MSK 2k4b/s MSK 1k2 & 2k4b/s
In transmit mode data transmission will start or finish (regardless of whether all data has been transmitted) immediately after the modem control bits are changed. To transmit a second data message the modem control bits must be set to '0', data bytes for the following message loaded, and the required bits set to '1'. When MSK receive is enabled bits 5 to 7 allow the detection of the MSK SYND, SYNC and SYNT frame sync patterns respectively. Each frame sync pattern may be individually controlled so any combination of the 3 patterns - SYND, SYNC (and it's inverse - SYNT) can be searched for. When transmitting MSK these bits should be set to '0' and the bit sync and frame sync patterns set in the first four 8 bit transfers from the host - see section 1.5.5. Bits 2 and 8 are reserved - set to '0'.
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D/881/7
PMR Signalling Processor
CMX881
Bits 11 to 9 determine the sub-audio transmission / reception signalling: Bit 11 0 0 0 0 1 1 1 1 Bit 10 0 0 1 1 0 0 1 1 Bit 9 0 1 0 1 0 1 0 1 Tx - Transmitted signal: No Sub-Audio Transmitted Inverted DCS* DCS Do not use CTCSS Do not use Do not use Do not use Rx - Monitored signal(s): No Sub-audio Monitoring Inverted DCS* DCS DCS + inv DCS* CTCSS CTCSS + inv DCS* CTCSS + DCS CTCSS + DCS + inv DCS*
* See Table 3 DCS Modulation Modes.
Bit 12 enables Audio tone generation (see section 1.6.14). This operates in transmit and receive modes. In transmit mode this bit will only enable the Audio Generator when no other voice band signals are being transmitted i.e. bits 14, 13, 4 and 3 set to '0'. Bits 14 and 13 determine the voice band tone transmission and reception. When transmitting or receiving audio band signals the voice path must be disabled by clearing `Voice Enable' bit 15 to '0'. Bit 14 0 0 1 1 Bit 13 0 1 0 1 Tx - Transmitted signal No voice band tone transmitted Selcall DTMF Reserved Rx - Monitored signal No voice band tones monitored Selcall Reserved Reserved
When set to '1', bit 15 enables the voice path. In transmit mode the selected audio input is routed to the modulator outputs. In receive mode the voice processing path is enabled to the audio output. In transmit mode bit 15, if set to '1', will be temporarily disabled (cleared to '0') whenever any of the bits 3, 4, 12, 13 and 14 are set to '1'. In receive mode bit 15, if set to '1', will be temporarily disabled (cleared to '0') whenever bit 12 is set to '1'. It is up to the host C to control bit 15 when voice band signals are received. The Mode Control register ($C1) may be written to at any time (subject to C-BUS timing restrictions). If the enable bit of the currently decoded signal is disabled whilst in phase 2 the CMX881 will return to phase 1 for that band. If the same signal needs to be searched for again then the appropriate bit needs to be set back to `1' in $C1. However, to de-emphasise Selcall tones, bit 15 must be set to `1'. The CMX881 will only detect signals when their amplitude is above the threshold set for each band (subaudio and voice), as set in the program registers. Therefore even if valid tones or signals are present the CMX881 will ignore them unless they exceed the detect threshold. Time and level hysteresis is applied to reduce chattering in marginal conditions. Detection strategies used by the CMX881 whilst in receive mode: When in receive mode the CMX881 treats the received signal in two bands; Sub-audio (60-260Hz) and voice band (300-3kHz). For the sub-audio the CMX881 can monitor and decode CTCSS and DCS signals in parallel. Because certain FFSK bit patterns can mimic some Selcall tones the Selcall receiver is temporarily disabled when an FFSK frame sync is detected. The host must monitor the received data and restore Selcall (by setting bits 14 and 13 as required) when it has detected the end of data.
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D/881/7
PMR Signalling Processor
CMX881
1.6.9 Bit:
$C2 AUDIO & CTCSS CONTROL: 16-bit write-only
15 0 14 0 13 0 12 11 10 9 8 7 0 6 0 5 4 3 2 1 0 Special Sub-Audio
Voice filter mode
CTCSS tone
Bits 5 to 0 select the CTCSS tone to be used in both Tx and Rx modes, the range of valid addresses is 039 (in decimal). In Tx this number will be used to select the CTCSS tone, if the tone number is outside the valid range no signalling will occur. In Rx this address will be searched for when CTCSS is enabled in the Mode register and if detected, this number will be indicated in the Tone Status register $CC. Bits 9 and 8 select special sub-audio tones in accordance with the following table. Selecting the `DCS turn off tone' during DCS transmit will cause the DCS turn off tone to be transmitted; this will override the DCS data being transmitted. `DCS turn off tone' must be selected in this register to enable detection of TM the DCS turn off tone during receive. If the Tone Clone mode is selected this allows the device in Rx to non-predictively detect any CTCSS frequency in the range of valid tones, the received tone number will be reported in the Tone Status register $CC. Bit 9 0 0 1 1 Bit 8 0 1 0 1 Freq (Hz) 134.4 Clone Special Sub-Audio tone None DCS turn off tone Reserved - do not set CTCSS Tone clone mode (Rx only)
The voice filter control bits 12 and 11 determine the Voice Band Filter mode applied to the voice signal before it is transmitted or after it has been received. Bit 10 controls the de-emphasis (Rx) or preemphasis (Tx) mode of the voice band filtering. Bit 12 X X 0 0 1 1 Bit 11 X X 0 1 0 1 Bit 10 0 1 X X X X Voice filter mode Disable de/pre-emphasis Enable de/pre-emphasis No filtering applied 12.5kHz channel filtering 25.0kHz channel filtering Reserved - do not use
Bits 15 to 13 and 7 to 6 are reserved - set to `0'. 1.6.10 Bit: $C3 Tx In-Band Tones: 16-bit write-only
15 14 13 12 11 10 0 9 0 8 0 7 0 6 0 5 Twist 4 Single 3 2 1 0 Tx Selcall tone Tx DTMF tone
Bits 15 to 11 define the tone transmitted when Tx Selcall is enabled. The frequency is as defined in Table 5 Selcall Tones. Bits 10 to 6 are reserved - set to `0'. Bit 5 controls DTMF twist, when set to '0' the two tones are sent at the same level, when set to '1' the amplitude of the lower frequency tone is 2dB below the amplitude of the higher tone. Bit 4 controls whether a single tone is generated when transmitting DTMF, when set to '0' dual tones are sent, when set to '1' the single tone identified in Table 8 is sent on it's own. Bits 3 to 0 define the signals produced when Tx DTMF is enabled. The frequencies are as defined in Table 8 DTMF Tone Pairs and Corresponding Tx Programming Codes. 1.6.11 $C7 Reserved - Do not write to this register
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D/881/7
PMR Signalling Processor
CMX881
1.6.12 Bit:
$C8 PROGRAMMING REGISTER: 16-bit write-only
15 First Word 14 Block Number 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Block / Data
Programming Data
See section 1.6.20 for a description of this register. 1.6.13 Bit: $CA TX DATA: 16-bit write-only
15 0 14 0 13 0 12 0 11 0 10 En CRC 9 Tx CRC 8 Last Data 7 6 5 4 3 2 1 0
Tx Data Byte
Bits 15 to 11 are reserved, set to '0'. Bits 10 to 8 control the MPT1327 compatible CRC / parity circuit: See section 1.5.5 for timing diagrams. En CRC (bit 10): Tx: This bit should be changed when updating this register with new data. If this bit is set to '0' the CRC / parity circuit will be reset, bits 7 to 0 will be passed to both the modulator and CRC / parity circuit after it has been reset. If set to '1' the CRC / parity circuit will not be reset and bits 7 to 0 will be passed to both the modulator and CRC / parity circuit. Rx: In receive this bit should be changed before the interrupt for the next over-air byte occurs. If this bit is set to '0' the next received byte will be passed to the CRC / parity circuit after it has been reset. If this bit is set to '1' the next received byte will be passed to the CRC / parity circuit which will not be reset. Tx CRC (bit 9): If this bit is set to '1' the Tx Data Byte (bits 7-0) is transmitted and also passed to the CRC and parity generator. The following 2 bytes transmitted are the 15 bits of CRC and the 1 bit of parity. The request to load more data into the CMX881 will be raised after the 2nd byte is passed to the modulator. Last Data (bit 8): If this bit is set to '1' then the CMX881 will ignore bits 7 to 0, finish transmitting the current byte, append a hang bit and then turn off the FFSK modulator. At the end of transmitting the hang bit the CMX881 will set bit 7 of the Status register to '1' and an interrupt (if enabled) will be raised, the host may then wait a short time before shutting down the rf sections of the transmit path. Tx Data Byte (bits 7 to 0) holds the next byte of MSK data to be transmitted. Outgoing data is continuous, whatever data is in bits 7 to 0 will be re-transmitted if the host does not provide required data in time. Transmission of current data will be completed before transmission of newly loaded data begins. 1.6.14 Bit: $CD AUDIO TONE: 16-bit write only
15 0 14 0 13 0 12 0 11 10 9 8 7 6 5 4 3 2 1 0 Audio Tone
When the required bits of the Mode Control register ($C1) are set an audio tone will be generated with the frequency determined by bits (11-0) of this register in accordance with the formula below: frequency = Audio Tone (i.e. 1Hz per LSB) If bits 11-0 are programmed with '0' no tone (i.e. Vbias) will be generated when the Audio Tone is enabled. The Audio Tone frequency must only be set to generate frequencies from 300Hz to 3000Hz. The host must suppress other data and set the correct audio routing before generating an audio tone and re-enable data and audio routing on completion of the audio tone. The timing of intervals between these actions is also controlled by the host C. This register may be written to whilst the audio tone is being generated, any change in frequency will take place after the C-BUS write to this register. This allows sequences (e.g. ring or alert tunes) to be generated for the local speaker (Tx or Rx via the AUDIO pin) or transmitted signal (via the MOD1/2 pins).
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D/881/7
PMR Signalling Processor
CMX881
1.6.15 Bit:
$CE INTERRUPT MASK: 16-bit write-only
15 IRQ MASK 14 0 13 Rx Selcall detect MASK 5 0 12 0 11 Rx CTCSS detect MASK 3 Rx 1200b/s detect MASK 10 9 8 Rx DCS Aux ADC High Aux ADC Low detect MASK MASK MASK 2 0 1 0 0 Prog Flag MASK
Bit:
7 Tx MSK end MASK
6 Data transfer MASK
4 Rx 2400b/s detect MASK
Bit 15 14 13
Value 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 1 0
12 11
10
9, 8 7 6 5 4 3 2,1 0
Function Enable selected interrupts Disable all interrupts (IRQN pin not activated) Reserved - Set to 0 Enable interrupt when a change to a Selcall tone is detected as indicated by a '0' to '1' change of bit 13 of the Status register Disabled Reserved - Set to 0 Enable interrupt when a change to a programmed CTCSS tone is detected as indicated by a '0' to '1' change of bit 11 of the Status register Disabled Enable interrupt on a change in the detect status of the DCS decoder as indicated by a '0' to '1' change of bit 10 of the Status register Disabled Enable interrupt when the corresponding Aux ADC status bit changes Disabled Enable interrupt when MSK data transmission has ended Disabled Enable interrupt when an MSK data transfer is required Disabled Reserved - Set to 0 Enable interrupt when a valid 2400b/s frame sync is detected Disabled Enable interrupt when a valid 1200b/s frame sync is detected Disabled Reserved - Set to 0 Enable interrupt when Prog Flag bit of the Status register changes from '0' to '1' (see Programming register $C8) Disabled
The following 4 registers are read only 1.6.16 Bit: $B4 AUX ADC MONITOR DATA: 8-bit read-only
7 6 5 4 3 2 1 0 Signal Monitor Data
This data holds the result of the last measurement performed by the auxiliary ADC. The signal processor must be on to read Aux ADC data, so Power Down Control register b5 must be set to `1'. This is independent of whether Tx or Rx modes are selected.
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D/881/7
PMR Signalling Processor
CMX881
1.6.17 Bit:
$C6 STATUS: 16-bit read-only
15 IRQ 14 0 13 Selcall state change 5 0 12 0 11 CTCSS state change 3 Rx 1200b/s 10 DCS state change 2 9 Aux ADC Monitor High 8 Aux ADC Monitor Low
Bit:
7 Tx MSK end
6 MSK data transfer required
4 Rx 2400b/s
1
0 Programming Flag
Rx data information
This word holds the current status of the CMX881: the value read out is only valid when bit 5 of the Power Down Control register ($C0) is set to '1'. Changes in the Status register will cause the IRQ bit (bit 15) to be set to '1' if the corresponding interrupt mask bit is enabled. An interrupt request is issued on the IRQN pin when the IRQ bit is '1' and the IRQ MASK bit (bit 15 of register $CE) is set to '1'. Bits 1 to 15 of the Status register are cleared to '0' after the Status register is read. Bit 0 is only cleared by writing to the Programming Register. Bits 14, 12 and 5 are reserved. Bits 13, 11 and 10 indicate that a Selcall, CTCSS or DCS event caused the interrupt, the host should then read the Tones Status register ($CC) for further information. In transmit these bits will be set to '0'. Detection of the DCS turn off tone and removal of DCS turn off tone are both flagged as DCS events in the Status register, not as CTCSS events. Aux ADC High (bit 9) and Aux ADC Low (bit 8) reflect the recent history of the Aux ADC level, with respect to the high and low thresholds. The most recent Aux ADC reading can be read from $B4. Aux ADC Monitor High 0 0 1 1 Aux ADC Monitor Low 0 1 0 1 Aux ADC history since last reading: Neither threshold crossed Signal gone below low threshold Signal gone above high threshold Signal gone below low threshold and above high threshold
In Tx mode bit 7 will be set when the last bit of MSK data has been transmitted. Note; this bit will only be set if bit 8 of the Tx Data register ($CA) is set at the appropriate time. In Rx mode this bit will be set to '0'. Bit 6 indicates that new transmit data is required (in Tx mode) or received data is ready to be read (in Rx mode). For continuous transmission or reception of information, a data transfer should be completed within the time appropriate for that data (see Table 9 Maximum Data Transfer Latency). Bits 4 and 3 indicate the received data rate after a valid frame sync pattern has been detected. Bits 2 and 1 indicate the received frame sync pattern detected. Bit 4 0 0 1 1 Bit 3 0 1 0 1 Data type none 1200b/s 2400b/s Reserved Bit 2 Bit 1 Received sync pattern: Reserved SYNC SYNT SYND
Reserved 0 0 0 1 1 0 1 1 Reserved
Programming Flag, bit 0: The Programming Register ($C8) should only be written to when bit 0 is set to '1' (with both Mode select bits set low - See register $C8). Writing to the Programming Register ($C8) clears bit 0 to '0'. Bit 0 is restored to '1' when the programming action is complete, normally within 250s, when it is then safe to write to the Programming Register.
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D/881/7
PMR Signalling Processor
CMX881
1.6.18 Bit:
$C5 RX DATA: 16-bit read-only
15 0 14 0 13 0 12 0 11 0 10 0 9 Rx CRC 8 0 7 6 5 4 3 2 1 0
Rx Data Byte
Bits 15 to 10 and 8 are reserved. Rx CRC (bit 9) indicates the validity of the received data bytes since the En CRC bit has been set, a `1' indicates a valid CRC and parity bit, a `0' indicates that the received CRC and parity bits do not match the locally calculated values - see section 1.5.5. Rx Data Byte (bits 7 to 0) holds the most recent byte of decoded MSK data. Received data is continuous, if the data is not read before the next data is received the current data will be over-written. 1.6.19 Bit: $CC TONES STATUS: 16-bit read-only
15 14 13 12 11 10 9 8 7 0 6 0 5 4 3 2 1 0 Detected Selcall tone frequency Sub-Audio Status Detected CTCSS code
This word holds the current status of the CMX881 sub-audio and Selcall sections. This word should be read by the host after an interrupt caused by a DCS, CTCSS or Selcall event. The value in bits 5 to 0, Detected CTCSS code, identifies the detected sub-audio tone by its position in Table 2 CTCSS Tones. If bits 5 to 0 = '000000' there is no CTCSS tone currently being detected. If bits 5 to 0 = '110111' (= 55 in decimal) this indicates that an Invalid Tone has been detected. An Invalid Tone is any tone in the subaudio band which is not the selected subaudio tone. A change in the state of bits 5-0 to Invalid Tone from the no tone condition will not cause Status register ($C6), b11 to be set to '1'. Any other change in the state of bits 5-0 will cause the Status register ($C6), b11 to be set to '1'. A detected Selcall frequency is indicated by the value in bits 15 to 11, `Detected Selcall tone frequency', identifies the frequency by its position in Table 5 Selcall Tones. If bits 15 to 11 = '00000' there is no Selcall tone currently being detected. A change in the state of bits 15 to 11 will cause bit 13 of the Status register ($C6), `Selcall State Change', to be set to '1'. Bits 10 to 8 indicate the DCS and special sub-audio tone status. The Status register ($C6) will indicate the type of signal detected. If DCS or special CTCSS tones are detected they will be indicated in bits 10 to 8 according to the table below and bits 5 to 0 will be set to '000000'. If a normal CTCSS tone is detected bits 10 to 8 will be set to '000' and bits 5 to 0 will indicate the decoded tone. A change in the state of bits 10 to 8 will cause the DCS state change bit of the Status register to be set to '1'. During DCS receive, the device can flag an interrupt when the DCS code fails to be recognised. This may be due to code dropout. The turn off tone may be flagged shortly after, if the transmission is ending. Alternatively the DCS link may be restored and DCS detection will be flagged again. Bit 10 0 0 0 0 1 1 1 1 Bit 9 0 0 1 1 0 0 1 1 Bit 8 0 1 0 1 0 1 0 1 Sub-Audio status No DCS or special CTCSS detected Reserved DCS sequence detected inverted DCS sequence detected Reserved 134.4Hz DCS turn off tone detected Reserved Reserved
Only enabled with DCS Only enabled with DCS Only enabled with DCS
When the relevant detection mode is not enabled, the associated bits will be set to '0'. In Tx mode this register will be set to '0'. Bits 7 and 6 are reserved. During DCS receive, the device can flag an interrupt when the DCS code fails to be recognised. This may be due to code dropout. The turn off tone may be flagged shortly after, if the transmission is ending. Alternatively the DCS link may be restored and DCS detection will be flagged again.
2004 CML Microsystems Plc 40 D/881/7
PMR Signalling Processor
CMX881
1.6.20
Bit:
$C8 PROGRAMMING REGISTER: 16-bit write-only
15 First Word 14 Block Num. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Block Num. or Data Programming Data
This register is used for programming various gains, levels, offset compensations, tones and codes. If the user programs any of these values then bit 4 of $C0 (Power Down Control) must be set to '1'. Following a C-BUS Reset or a Power Up Reset, the programmed values are initialised in accordance with the settings described in section 1.6.2 (C-BUS Reset). The Signal Processing function and the XTAL clock circuit must both be enabled in order to write to the Programming Register, so Power Down Control register bit 5 must be set to '1' and bit 3 must be set to '0'. The Programming Register should only be written to when the Programming Flag bit (bit 0) of the Status register is set to '1' and the Rx and Tx modes are disabled (bits 0 and 1 of the Mode Control register both '0'). The Programming Flag is cleared when the Programming Register is written to. When the corresponding programming action has been completed (normally within 250s) the CMX881 will set the flag back to '1' to indicate that it is now safe to write the next programming value. The Programming Register must not be written to while the Programming Flag bit is '0'. Programming is done by writing a sequence of 16-bit words to the Programming Register, in the order shown in the following tables. Writing data to the Programming Register must be performed in the order shown for each of the blocks, however the order in which the blocks are written is not critical. If later words in a block do not require updating the user may stop programming that block when the last change has been performed. e.g. If only 'Fine output gain 1' needs to be changed the host will need to write to P4.0, P4.1 and P4.2 only. The user must not exceed the defined word counts for each block. The word P4.8 is allocated for production testing and must not be accessed in normal operation. The high order bits of each word define which block the word belongs to, and if it is the first word of that block: Bit 15 1 0 X X X X X Bit 14 X X 1 1 1 1 0 Bit 13 X X 0 0 1 1 Bit 12 X X 0 1 0 1 Write to Bit 11 - Bit 0 1 data for each block nd 2 and following data Write to block 0 (12 bit words) Write to block 1 (12 bit words) Write to block 2 (12 bit words) Reserved - do not use block 4 (14 bit words)
st
Block 0 - Modem Configuration:
Bit: P0.0 P0.1 P0.2 P0.3 15 1 0 0 0 14 1 1 1 1 13 0 0 0 0 12 0 0 0 0 11 10 0 0 0 0 9 8 7 6 5 4 3 2 1 0
MSK SYNC / SYNT LSB MSK SYNC / SYNT MSB MSK SYND LSB MSK SYND MSB
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CMX881
Block 1 -Selcall Setup:
Bit: P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P1.14 P1.15 P1.16 P1.17 P1.18 15 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 12 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0 Emph Selcall detect bandwidth
Audio band Tx level Audio band detect threshold
Programmable Selcall Repeat Tone Programmable Selcall Tone 0 Programmable Selcall Tone 1 Programmable Selcall Tone 2 Programmable Selcall Tone 3 Programmable Selcall Tone 4 Programmable Selcall Tone 5 Programmable Selcall Tone 6 Programmable Selcall Tone 7 Programmable Selcall Tone 8 Programmable Selcall Tone 9 Programmable Selcall Tone 10 Programmable Selcall Tone 11 Programmable Selcall Tone 12 Programmable Selcall Tone 13 Programmable Selcall Tone 14 Programmable Selcall Tone 15
Block 2 - CTCSS and DCS Setup:
Bit: P2.0 P2.1 P2.2 P2.3 P2.4 15 1 0 0 0 0 14 1 1 1 1 1 13 1 1 1 1 1 12 0 0 0 0 0 Sub-audio drop out time
DCS 24
11
10
9
8
7
6
5
4
3
2
1
0
CTCSS and DCS Tx level 0 CTCSS and DCS detect threshold DCS Code bits 11 - 0 DCS Code bits 23/22 - 12 0 CTCSS detect bandwidth
Block 3 - Reserved. Do not use.
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CMX881
Block 4 - Gain and Offset Setup:
Bit: P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 P4.6 P4.7 P4.8 15 1 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Fine Input Gain Reserved - set to '0' Fine Output Gain 1 Fine Output Gain 2 Output 1 Offset Control Output 2 Offset Control Ramp Rate Control Limiter Setting (all 1's = Vbias +/- 0.5 Vdd) Special Programming Register (Production Test Only)
1.6.20.1 PROGRAMMING REGISTER Block 0 - Modem Configuration: $C8 (P0.0-3)
Bit: P0.0 P0.1 P0.2 P0.3 15 1 0 0 0
MSK Frame SYNC / SYNT and SYND
14 1 1 1 1 13 0 0 0 0 12 0 0 0 0 11 10 0 0 0 0 9 8 7 6 5 4 3 2 1 0 MSK SYNC / SYNT LSB MSK SYNC / SYNT MSB MSK SYND LSB MSK SYND MSB
Bits 7 to 0 set the three 16-bit Frame Sync patterns used in Rx MSK data. Bit 7 of the MSB is compared to the earliest received data. Note: SYNT is the bitwise inverse of SYNC. After a power on reset SYNC is set to $C4D7 (MPT) and SYND is set to $B433 (PAA).
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D/881/7
PMR Signalling Processor
CMX881
1.6.20.2 PROGRAMMING REGISTER Block 1 - Selcall Setup: $C8 (P1.0)
Bit: P1.0 15 1
Voice band tones Tx Level
14 1 13 0 12 1 11 10 9 8 7 6 5 4 3 2 1 0 Emph Voice band tones Tx level
Bits 11 (MSB) to 1 (LSB) set the transmitted Selcall, DTMF, Audio Tone and MSK signal level (pk-pk) with a resolution of VDD(A)/2048 per LSB (1.465mV per LSB at VDD(A)=3V). Valid range for this value is 0 to 1536. Bit 0 controls Rx Selcall de-emphasis. When set to '0' the signal going to the Selcall tone detector is not de-emphasised. When voice processing is enabled in the Mode register, de/pre-emphasis is enabled in the Audio & Device Address register and this bit (b0) is set to '1', signals going to the Secall tone detector are de-emphasised in accordance with Figure 6. $C8 (P1.1)
Bit: P1.1 15 0
Selcall Detect Bandwidth and Audio Band Detect Threshold
14 1 13 0 12 1 11 0 10 9 8 7 6 5 4 3 2 1 0 Audio band detect threshold Selcall detect bandwidth
The `detect threshold' bits (bits 9 to 4) set the minimum Selcall and/or MSK signal level that will be detected. The levels are set according to the formula: Minimum Level = Detect Threshold x 3.63mV rms at VDD(A) = 3V The Selcall detected bandwidth is set in accordance with the following table: Bit 3 1 1 Recommended for EEA 1 1 Bit 2 0 0 0 0 Bit 1 0 0 1 1 Bit 0 0 1 0 1 BANDWIDTH Will Decode Will Not Decode 1.1% 2.4% 1.3% 2.7% 1.6% 2.9% 1.8% 3.2%
$C8 (P1.2-18) Programmable Selcall Tones
Bit: P1.2-18 15 0 14 1 13 0 12 1 11 0 10 9 8 7 6 5 4 3 2 1 0 Programmable Selcall Tone N (see below) R (see below)
These words set the programmable Selcall tones used in transmit and receive. The frequency is set in bits 11-0 for each word according to the formula: N = Integer part of (0.042666 x frequency) R = (0.042666 x frequency - N) x 6000 / frequency (round to nearest integer) Example: For 1010Hz, N = 43, R = 1. The programmed tones must only be set to frequencies from 400Hz to 3000Hz.
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D/881/7
PMR Signalling Processor
CMX881
1.6.20.3 PROGRAMMING REGISTER Block 2 - CTCSS and DCS Setup: $C8 (P2.0)
Bit: P2.0 15 1
CTCSS and DCS TX LEVEL
14 1 13 1 12 0 11 10 9 8 7 6 5 4 3 2 1 0 CTCSS and DCS Level
Bits 11 (MSB) to 0 (LSB) set the transmitted CTCSS or DCS sub-audio signal level (pk-pk) with a resolution of VDD(A)/16384 per LSB (0.183mV per LSB at VDD(A)=3V, giving a range 0 to 749.8mV pkpk). $C8 (P2.1)
Bit: P2.1 15 0
CTCSS TONE BW AND LEVEL
14 1 13 1 12 0 11 DCS 24 10 0 9 8 7 6 5 4 3 2 1 0 CTCSS and DCS detect threshold CTCSS detect bandwidth
Bit 11, DCS 24, sets the length of DCS code transmitted or searched for. When this bit is set to `1' 24 bit codes are transmitted and decoded. When this bit is set to `0' 23 bit codes are used. The `detect threshold' bits (bits 9 to 4) set the minimum CTCSS or DCS signal level that will be detected. The levels are set according to the formula: Minimum Level = Detect Threshold x 2mV rms at VDD(A) = 3V The CTCSS detected tone bandwidth is set in accordance with the following table: Bit 3 0 0 1 Recommended for CTCSS 1 1 1 $C8 (P2.2-3)
Bit: P2.2 P2.3 15 0 0
Bit 2 1 1 0 0 0 0
Bit 1 1 1 0 0 1 1
Bit 0 0 1 0 1 0 1
BANDWIDTH Will Decode Will Not Decode 0.5% 1.8% 0.8% 2.1% 1.1% 2.4% 1.3% 2.7% 1.6% 2.9% 1.8% 3.2%
DCS CODE (LOWER) and DCS CODE (UPPER)
14 1 1 13 1 1 12 0 0 11 10 9 8 7 6 5 4 3 2 1 0 DCS Data (bits 11-0) DCS Data (bits 23/22-12)
These words set the DCS code to be transmitted or searched for. The least significant bit (bit 0) of the DCS code is transmitted or compared first and the most significant bit is transmitted or compared last. Note that DCS Data bit 23 is only used when bit 11 (DCS 24) of P2.1 is set to `1'. $C8 (P2.4)
Bit: P2.4 15 0
SUBAUDIO DROP OUT TIME
14 1 13 1 12 0 11 10 9 8 7 6 5 4 0 3 2 1 0 Subaudio Drop Out Time
The Subaudio Drop Out Time defines the time that the sub-audio signal detection can drop out before loss of sub-audio is asserted. The period is set according to the formula: Time = Subaudio Drop Out Time x 8.0ms [range 0 to 120ms] The setting of this register defines the maximum drop out time that the device can tolerate. The setting of this register also determines the de-response time, which is typically 40ms longer than the programmed drop out time. 1.6.20.4 PROGRAMMING REGISTER Block 3 - Reserved
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D/881/7
PMR Signalling Processor
CMX881
1.6.20.5 PROGRAMMING REGISTER Block 4 - Gain and Offset Setup $C8 (P4.0)
Bit: P4.0 15 1
FINE INPUT GAIN
14 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fine Input Gain (unsigned integer)
Gain = 20 x log([32768-IG]/32768)
IG is the unsigned integer value in the `Fine Input Gain' field
Fine input gain adjustment should be kept within the range 0 to -3.5dB. $C8 (P4.1)
Bit: P4.1 15 0
Reserved
14 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved - set to '0'
This register is reserved and should be set to '0'. $C8 (P4.2-3)
Bit: P4.2 P4.3 15 0 0
FINE OUTPUT GAIN 1 and FINE OUTPUT GAIN 2
14 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Fine Output Gain 1 (unsigned integer) Fine Output Gain 2 (unsigned integer)
Gain = 20 x log([32768-OG]/32768)
OG is the unsigned integer value in the `Fine Output Gain' field
Fine output gain adjustment should be kept within the range 0dB to -3.5dB. $C8 (P4.4-5)
Bit: P4.4 P4.5 15 0 0
OUTPUT 1 OFFSET and OUTPUT 2 OFFSET
14 0 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2's complement offset for MOD_1, resolution = VDD(A)/16384 per LSB 2's complement offset for MOD_2, resolution = VDD(A)/16384 per LSB
Can be used to compensate for inherent offsets in the output path via MOD_1 (Output 1 Offset) and MOD_2 (Output 2 Offset). It is recommended that the offset correction is kept within the range +/-50mV. $C8 (P4.6)
Bit: P4.6 15 0
RAMP RATE CONTROL
14 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Ramp Rate Up Control (RRU) Ramp Rate Down control (RRD)
The ramp-up rate and ramp-down rates can be independently programmed. The ramp rates apply to all the analogue output ports. They only affect those ports being turned on (ramp-up) or turned off (ramp down). The ramp rates should be programmed before ramping any outputs. Time to ramp-up to full gain = Time to ramp down to zero gain = $C8 (P4.7)
Bit: P4.7 15 0
(1 + RRU) x 1.333ms (1 + RRD) x 1.333ms
TRANSMIT LIMITER CONTROL
14 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Limiter Setting, resolution = VDD(A)/16384 per LSB
This unsigned number sets the clipping point (maximum deviation from the centre value) for the MOD_1 and MOD_2 pins. The maximum setting ($2000) is +/- VDD(A)/2 i.e. output limited from 0 to VDD(A). Any settings above $2000 will limit to the $2000 setting. The limiter is set to maximum following a CBUS Reset or a Power Up Reset. The limiter is only applied to voice signals, not internally generated audio band signals. The levels of internally generated signals must be limited by setting appropriate transmit levels. $C8 (P4.8) Special Programming Register - do not access.
46 D/881/7
2004 CML Microsystems Plc
PMR Signalling Processor
CMX881
1.7 Application Notes
R a dio S e ction Rx D e m od u la to r RF 2-p oin t T x M o du lator
D iscrim in ato r inp ut
R eceive F FS K V oice+ SubA udio
A udio ou tpu t
M od ula tor ou tpu t 1
CM X881
T ransm it
A udio inpu t 1
M od ula tor ou tpu t 2
M IC 1
F FS K V oice+ SubA udio
A udio inpu t 2
M IC 2
C -B U S D isp lay D a ta P o rt H o st M icro C o ntro lle r K e yp ad
Figure 13 Possible PMR Configuration 1.7.1 CRC and Parity information
15 bit CRC is used with the inbuilt data packeting with the following generator polynomial: x
15
+x +x +x +x+x +x
14
13
11
4
2
0
A 15 bit remainder is calculated for previous bytes sent. When the CMX881 is instructed to send the CRC these 15 bits are added onto the end of the message with the least significant bit inverted. The 16 bit of the checksum is an even parity bit calculated from the message data and 15 bit CRC result (including the inverted last bit of the CRC). In receive the 15 bit CRC is calculated and even parity is generated at each byte boundary. If the calculated receive CRC is zero and the parity bits match the CRC bit is set to indicate a correctly decoded message.
th
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D/881/7
PMR Signalling Processor
CMX881
1.8 Performance Specification
1.8.1 Electrical Performance
The performance data are target figures, that may change subject to the outcome of device evaluation. Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. -0.3 -0.3 -0.3 -0.3 -30 -20 0 0 Max. 7.0 7.0 VDD(D) + 0.3 VDD(A) + 0.3 +30 +20 0.3 50 Unit V V V V mA mA V mV
Supply: VDD(D)- VSS(D) VDD(A)- VSS(A) Voltage on any pin to VSS(D) Voltage on any pin to VSS(A) Current into or out of VDD(A), VSS(A), VDD(D) and VSS(D) Current into or out of any other pin Voltage differential between power supplies: VDD(D) and VDD(A) VSS(D) and VSS(A)
D6 Package (SSOP) Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature
Min. -55 -40 Min. -55 -40
Max. 550 9 +125 +85
Unit mW mW/C C C
E1 Package (TSSOP) Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature
Max. 400 5.3 +125 +85
Unit mW mW/C C C
Operating Limits Correct operation of the device outside these limits is not implied. Notes Supply (VDD - VSS) Operating Temperature Clock/Xtal Frequency Notes: 11 11 Min. 2.7 -40 18.3 Max. 5.5 +85 18.6 Unit V C MHz
Nominal clock frequency is 18.432MHz.
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D/881/7
PMR Signalling Processor
CMX881
Operating Characteristics For the following conditions unless otherwise specified: External components as recommended in Figure 2. Maximum load on digital outputs = 30pF. Xtal Frequency = 18.432MHz 0.01% (100ppm). VDD = 2.7V to 5.5V; Tamb = -40C to +85C. Reference Signal Level = 308mV rms at 1kHz with VDD = 3V. Signal to Noise Ratio (SNR) in bit rate bandwidth. Input stage gain = 0dB. Output stage attenuation = 0dB. DC Parameters Supply Current IDD(D) (VDD = 3.0V) IDD(A) (VDD = 3.0V) IDD(D) (All Power-saved) (VDD = 3.0V) IDD(A) (All Power-saved) (VDD = 3.0V) C-BUS Interface Input Logic `1' Input Logic `0' Input Leakage Current (Logic `1' or `0') Input Capacitance Output Logic `1' (IOH = 120A) Output Logic `0' (IOL = 360A) "Off" State Leakage Current IRQN (Vout = VDD(D)) REPLY_DATA (output HiZ) CLOCK_OUT Output Logic `1' Output Logic `0' CLOCK/XTAL Input Logic `1' Input Logic `0' Input current (Vin = VDD) Input current (Vin = VSS) VBIAS Output voltage offset wrt VDD/2 (IOL < 1A) Output impedance Notes: 21 22 23 (IOH = 120A) (IOH = 1mA) (IOL = 360A) (IOL = -1.5mA) 22 70% -40 23 -2% 22 +2% VDD k 30% 40 VDD VDD A A Notes 21 21 21 21 70% -1.0 90% -1.0 -1.0 90% 80% 10% 15% 30% 1.0 7.5 10% 10 1.0 1.0 Min. Typ. 4.5 1.0 2.0 2.0 Max. 8.0 2.0 10 10 Unit mA mA A A VDD VDD A pF VDD VDD A A A VDD VDD VDD VDD
Not including any current drawn from the device pins by external circuitry. Characteristics when driving the CLOCK/XTAL pin with an external clock source. Applies when utilising VBIAS to provide a reference voltage to other parts of the system. When using VBIAS as a reference, VBIAS must be buffered. VBIAS must always be decoupled with a capacitor as shown in Figure 2.
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D/881/7
PMR Signalling Processor
CMX881
AC Parameters CLOCK/XTAL Input 'High' pulse width 'Low' pulse width Input impedance (at 18.432MHz) Powered-up Resistance Capacitance Powered-down Resistance Capacitance Clock frequency Clock stability/accuracy Clock start up (from power-save) CLOCK_OUT Output CLOCK/XTAL input to CLOCK_OUT timing: (in high to out high) (in low to out low) 'High' pulse width 'Low' pulse width VBIAS Start up time (from power-save) Microphone, Input_2 and Disc Inputs (MIC, INPUT_2, DISC) Input impedance Input signal range Load resistance (pin 12, 14 and 16) Amplifier open loop voltage gain (I/P = 1mV rms at 100Hz) Unity gain bandwidth Programmable Input Gain Stage Gain (at 0dB) Cumulative Gain Error (wrt attenuation at 0dB) Notes: 31 32 33 34 35 36
Notes 31 31
Min. 21 21
Typ.
Max.
Unit ns ns
150 20 300 20 18.432 100 400
k pF k pF MHz ppm ms
32 32 33 33
22 22
15 15 27.13 27.13 30
33 33
ns ns ns ns ms
34 35
1 10 80 60 1.0 90
M %VDD k dB MHz
36 -0.5 -1.0 0 0.5 1.0 dB dB
Timing for an external input to the CLOCK/XTAL pin. CLOCK/XTAL input driven by external source. 18.432MHz XTAL fitted. With no external components connected After multiplying by gain of input circuit, with external components connected. Gain applied to signal at output of buffer amplifier, pin 12, 14 or 16
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PMR Signalling Processor
CMX881
AC Parameters (cont.) Modulator Outputs 1 and 2 and Audio Output (MOD_1, MOD_2, AUDIO) Power-up to output stable Modulator Attenuators Attenuation (at 0dB) Cumulative Attenuation Error (wrt attenuation at 0dB) Output Impedance Enabled Disabled Audio Attenuator Attenuation (at 0dB) Cumulative Attenuation Error (wrt attenuation at 0dB) Output Impedance Enabled Disabled Feedback load resistance Amplifier open loop voltage gain (I/P = 1mV rms at 100Hz) Unity gain bandwidth Notes: 37
Notes
Min.
Typ.
Max.
Unit
37 -0.2 -0.6 38 38 -0.5 -1.0 38 38 80
50 0
100 0.2 0.6
s dB dB k dB dB k k dB MHz
600 500 0 0.5 1.0 600 500
60 1.0
38
Power-up refers to issuing a C-BUS command to turn on an output. These limits apply only if VBIAS is on and stable. At power supply switch-on, the default state is for all blocks, except the XTAL and C-BUS interface, to be in placed in powersave mode. Small signal impedance, at VDD = 3.0V and Tamb = 25C.
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PMR Signalling Processor
CMX881
AC Parameters (cont.) Auxiliary ADC (Signal Monitor) 8 Bit ADC Mode Resolution Input Range Conversion time Input impedance Resistance Capacitance Zero error (input offset to give ADC output = 0) Integral Non-linearity Differential Non-linearity Source output impedance Level Threshold Detect Mode Threshold Resolution Upper threshold range (VTH) Lower threshold range (VTL) Signal Monitor change to IRQ Signal Monitor change to Receiver-TurnOn Notes: 41 42 43 44 45 46 47
Notes
Min.
Typ.
Max.
Unit
8 10% 41 20.8 10 5 -20 42 43 42 43 44 8 45 45 46 47 VTL VSS(A) VDD(A) VTH 120 60 +20 2 4 1 3 24 90%
Bits VDD(A) s M pF mV LSB LSB LSB LSB k Bits V V s s
With clock frequency of 18.432MHz. Vdd(A) >= 3.0V. Vdd(A) < 3.0V. Denotes output impedance of the driver of the Signal Monitor input, to ensure < 1 bit additional error under nominal conditions. Upper threshold > Lower threshold Time from Signal Monitor input rising above Upper Threshold or falling below Lower Threshold, to IRQN being asserted. Time from Signal Monitor input rising above Upper Threshold to receiver path powering up, settling and starting automatic signal type identification.
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PMR Signalling Processor
CMX881
AC Parameters (cont.) Receiver Signal Type Identification Probability of correctly identifying signal type (SNR = 12dB) CTCSS Detector Sensitivity Response Time De-response Time Dropout immunity Frequency Range SELCALL Detector Sensitivity Response Time De-response Time Dropout immunity Frequency Range DCS Decoder Sensitivity Bit-Rate Sync Time FFSK/MSK Decoder Signal Input Dynamic Range Bit Error Rate (SNR = 20dB) Receiver Synchronisation (SNR = 12dB) Probability of bit 16 being correct (Pure Tone) (Composite Signal) (Composite Signal)
Notes
Min.
Typ.
Max.
Unit
>>99.9 51 52 52, 55 55 60 -26 140 210 160
% dB ms ms ms Hz dB ms ms ms Hz mVp-p edges 800 mVrms -8 10 %
250 260
(Pure Tone) (Good Signal) (Good Signal) (Selcall)
53
-26 35 400 45 20 3000
51
58 2
54 54
100 <1 >99.9
Notes:
51 52 53 54 55
Sub-Audio Detection Level threshold set to 16mV. Composite signal = 308mV rms at 1kHz + 75mV rms Noise + 31mV rms SubAudio signal. Noise bandwidth = 5kHz Band Limited Gaussian. Selcall Tone Detection Level threshold set to 16mV. VDD (A) = 3.0V, for a "101010101 ... 01" pattern measured at the input amplifier feedback pin (12). Signal level scales with VDD (A). See Figure 15 for variation of BER with SNR. With sub-audio dropout time (P2.4) set to 120ms. The typical dropout immunity is approximately 40ms more than the programmed dropout immunity. The typical de-response time is approximately 90ms longer than the programmed dropout immunity. See section 1.6.20.3, P2.4
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D/881/7
PMR Signalling Processor
CMX881
AC Parameters (cont.) CTCSS Encoder Frequency Range Tone Frequency Accuracy Tone Amplitude Tolerance Total Harmonic Distortion Selcall Encoder Frequency Range Tone Frequency Accuracy Tone Amplitude Tolerance Total Harmonic Distortion DTMF Encoder Output signal level Output distortion DCS Encoder Bit Rate Amplitude Tolerance FFSK/MSK Encoder Output signal level Output level variation Output distortion rd 3 harmonic distortion Logic 1 freq 1200baud and 2400baud Logic 0 freq 1200baud 2400baud Isochronous distortion (0 to 1 and 1 to 0) High tone Low tone
Notes
Min. 60.0
Typ.
Max. 260 0.3 +1.0 4.0 3000 0.3 +1.0 4.0
Unit Hz % dB % Hz % dB % dB dB dB % bits/s dB mVrms dB % % Hz Hz Hz s
61 62
-1.0 2.0 400
63 62
-1.0 2.0 0 -2 0 2 134.4
(twist on) (twist off)
64 64
5
61
-1.0 775 -1.0 1198 1798 2398 1200 1800 2400
+1.0
+1.0 5 3 1202 1802 2402 40
Notes:
61 62 63 64
VDD(A) = 3.0V and TX Sub-Audio Level set to 88mV p-p (31mV rms). Measured at MOD_1 or MOD_2 output. VDD(A) = 3.0V and Tx Audio Level set to 871mV p-p (308mV rms). With respect to high tone level
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D/881/7
PMR Signalling Processor
CMX881
AC Parameters (cont.) Analogue Channel Audio Filtering Pass-band (nominal bandwidth): Received voice 12.5kHz channel transmitted voice 25kHz channel transmitted voice Pass-band Gain (at 1.0kHz) Pass-band Ripple (wrt gain at 1.0kHz) Stop-band Attenuation Residual Hum and Noise Pre-emphasis De-emphasis
Notes
Min.
Typ.
Max.
Unit
71 72 73
300 300 300 0 -2 33.0
3000 2550 3000 +0.5 -50 6 -6
76 74 75
Hz Hz Hz dB dB dB dBp dB/oct dB/oct
Notes:
71 72 73 74 75 76
The receiver voice filter complies with the characteristic shown in Figure 5. The high pass filtering removes sub-audio components from the audio signal. The 12.5kHz channel filter complies with the characteristic shown in Figure 9. The 25kHz channel filter complies with the characteristic shown in Figure 8. The pre-emphasis filter complies with the characteristic shown in Figure 10. The de-emphasis filter complies with the characteristic shown in Figure 6. dBp represents a psophometrically weighted measurement.
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PMR Signalling Processor
CMX881
C-BUS Timing
Figure 14 C-BUS Timing C-BUS Timing tCSE CSN Enable to SClk high time tCSH Last SClk high to CSN high time SClk low to ReplyData Output Enable tLOZ Time tHIZ CSN high to ReplyData high impedance CSN high time between transactions tCSOFF Inter-byte time tNXT SClk cycle time tCK SClk high time tCH SClk low time tCL Command Data setup time tCDS Command Data hold time tCDH Reply Data setup time tRDS Reply Data hold time tRDH Notes: Notes Min. 100 100 0.0 1.0 200 200 100 100 75 25 50 0 Typ. Max. Unit ns ns ns s s ns ns ns ns ns ns ns ns
1.0
1. Depending on the command, 1 or 2 bytes of COMMAND DATA are transmitted to the peripheral MSB (Bit 7) first, LSB (Bit 0) last. REPLY DATA is read from the peripheral MSB (Bit 7) first, LSB (Bit 0) last. 2. Data is clocked into the peripheral on the rising SERIAL_CLOCK edge. 3. Commands are acted upon at the end of each command (rising edge of CSN). 4. To allow for differing C serial interface formats C-BUS compatible ICs are able to work with SERIAL_CLOCK pulses starting and ending at either polarity. 5. Maximum 30pF load on IRQN pin and each C-BUS interface line.
These timings are for the latest version of C-BUS and allow faster transfers than the original C-BUS timing specification. The CMX881 can be used in conjunction with devices that comply with the slower timings, subject to system throughput constraints.
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PMR Signalling Processor
CMX881
1.0E-01
1.0E-02
1.0E-03
2400 b/s 1.0E-04 1200 b/s
1.0E-05 4 5 6 7 8 9 10 11 12 13 14 SNR (dB) - Noise in bit rate bandwidth
Figure 15 Typical FFSK/MSK Bit Error Rate Graph
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PMR Signalling Processor
CMX881
1.8.2 Packaging
Figure 16
Mechanical Outline of 28-pin SSOP (D6): Order as part no. CMX881D6
Figure 17
Mechanical Outline of 28-pin TSSOP (E1): Order as part no. CMX881E1
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D/881/7
PMR Signalling Processor
CMX881
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.
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No 2 Kallang Pudding Road, #09 to 05/06 Mactech Industrial Building, Singapore 349307
No. 218, Tian Mu Road West, Tower 1, Unit 1008, Shanghai Kerry Everbright City, Zhabei, Shanghai 200070, China. Tel: +86 21 6317 4107 +86 21 6317 8916 Fax: +86 21 6317 0243 Sales: cn.sales@cmlmicro.com.cn Technical Support: sg.techsupport@cmlmicro.com
Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 Sales: sales@cmlmicro.com Technical Support: techsupport@cmlmicro.com
Tel: +1 336 744 5050, 800 638 5577 Fax: +1 336 744 5054 Sales: us.sales@cmlmicro.com Technical Support: us.techsupport@cmlmicro.com
Tel: +65 6745 0426 Fax: +65 6745 2917 Sales: sg.sales@cmlmicro.com Technical Support: sg.techsupport@cmlmicro.com
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